What's Changed

• SmbusIntelSkylakeIMC: Support all addresses, remove special case hand… by @CalcProgrammer1 in #62
• Add Zhaoxin MSR module by @a1ive in #64
• Fix DellSMM single-native bug making the module unusable

Full Changelog: 0.2.8...0.2.9

What's Changed

• Allow additional ports 0x25c and 0x25d in is_port_allowed for EC mailbox by @Undervoltologist in #58
• Improve performance of Skylake SMBus. by @Blacktempel in #60

New Contributors

• @Undervoltologist made their first contribution in #58

Full Changelog: 0.2.7...0.2.8

What's Changed

• AMD RyzenSmu updates and fixes by @irusanov in #56
• Add I2C_SMBUS_I2C_BLOCK_DATA for SmbusI801 by @Blacktempel in #55
• IntelMSR: allow read/write of MSR_VR_CURRENT_CONFIG (0x601) by @Marki4175 in #59

New Contributors

• @Marki4175 made their first contribution in #59

Full Changelog: 0.2.6...0.2.7

What's Changed

• Add Intel MCHBAR read module by @a1ive in #54

Full Changelog: 0.2.5...0.2.6

What's Changed

• Allow reading uncore perf MSRs 0x620 and 0x621 in IntelMSR module by @DevTechProfile in #52

Full Changelog: 0.2.4...0.2.5

What's Changed

• LpcCrOSEC: Fix unexpected extra reads/writes by @Steve-Tech in #51
• Add Dell SMM module
• Add "sleep mode" to the SMBUS modules to reduce CPU usage if latency is not crucial
• Add MSR write to IntelMSR module, allowing writes to package power limits and OC mailbox

Full Changelog: 0.2.3...0.2.4

What's Changed

• AMD: Add missing codenames in SMU cmd cases by @irusanov in #48
• LpcCrOSEC: Add MEC support by @Steve-Tech in #46
• Add SMBus for Intel Skylake IMC (e.g. X299 Chipset) by @Blacktempel in #47

Full Changelog: 0.2.2...0.2.3

What's Changed

• Add MSR_IA32_MPERF and MSR_IA32_APERF to allowed MSRs by @DevTechProfile in #44
• RyzenSMU: Add Z2 Extreme to StrixPoint models by @irusanov in #41
• AMD: Add CSTATE MSR and allow write to more registers by @irusanov in #45

New Contributors

• @DevTechProfile made their first contribution in #44

Full Changelog: 0.2.1...0.2.2

What's Changed

• Add MSRs by @a1ive in #37
• Allow send SMU commands, read and write SMU registers by @Erruar in #38

New Contributors

• @a1ive made their first contribution in #37

Full Changelog: 0.2.0...0.2.1

Starting with this release, the minor version will be bumped to clarify the lack of API stability guarantee across releases. Since the modules are bundled with the software using them, this shouldn't cause issues as all updates are explicit to downstream users.

What's Changed

• AMD MSRs by @irusanov in #28
• AMD: Allow family 1Ah, add CPPC MSRs, support more codenames by @irusanov in #29
• Fixed low-high base Power Table address handling. Added 0x1Ah CPUs by @Erruar in #33
• Isa Bridge EC by @namazso in #26

New Contributors

• @irusanov made their first contribution in #28
• @Erruar made their first contribution in #33

Full Changelog: 0.1.6...0.2.0