Gigabyte EC#26
Conversation
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I have a Gigabyte Z790 UD/i5-12600KF, let me know what/how to test |
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If it’s not a machine you use / care about then just an RDP with admin would work, and I figure out the rest. Otherwise, I can prepare a test binary to see how far we get, and hopefully it won’t devolve into poking at random stuff in RWEverything. |
It's your personal machine, so a test binary would be preferable. |
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Running FaceIT AC by any chance? |
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Hi there |
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have Gigabyte AMD X670E with IT8792E as my main machine... willing to test with binaries if needed |
@namazso I use FaceIT AC. Is there a workaround? I recently got the defender issue with winring (openrgb and fancontrol) and I saw that in the new versions they use pawnio. My MB is an Asus Z170-k. |
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@yqfQiQkH0OhC5 short of uninstalling / unloading faceit, no, not for now. I guess you could write them in hopes of whitelisting, but likely the same signer also signed some vulnerable drivers at some point. So a solution from this side needs to wait for me to get another signer which will take a bit of time. |
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@namazso Thanks for your efforts and your time. I'm looking forward to that. |
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Is there any chance that Asus motherboard e.g. TUF B850 also not fully supported by PawnIO? I had installed PawnIO and together with FanControl. But it couldn't detect any motherboard fan controllers. |
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@simy1129 It is intended to be supported. The only intentional regression is losing the ability to control MB fans on Gigabyte, and restoring that is what this PR is about. Everything else is a bug in something that is intended to work, and should be reported as such. |
Try reaching out to HYTE. They told me when the WinRing0 stuff first started becoming an issue that they were considering signing a modified WinRing0 that only allowed admin apps access. If anyone was willing to sign a replacement for WinRing0 I would think they would be the ones. |
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@CalcProgrammer1 This is being tracked at namazso/PawnIO.Setup#1 and a solution might be on the horizon. The complicated licensing model of PawnIO is meant to subsidize a proper signing certificate. However, I'll keep HYTE in mind if anything falls through. |
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Hi, As a long time user of FanControl (and therefore LibreHardwareMonitor indirectly) I might be able to help test this issue. I have a GIGABYTE X870E AORUS PRO (with ITE IT8696E/AX + ITE IT87952E Combo SuperIO chips) which was working well with the older version of FanControl. Now I have incomplete Fan Control in that FanControl v240 can see and monitor all the fan headers, I can only control around half of them. The ones that don't fully work no longer respond to fan speed inputs. If I can be of help, please let me know. You can use Signal via SimonZerafa.64 or Mastodon via SimonZerafa@Infosec.Exchange to contact me, or via this thread. Kind Regards Simon Zerafa |
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Sorry, I was a bit busy dealing with other stuff. Here's a test program based on this current branch: untitled5.zip Run from terminal, as admin, and copy output (or you can also redirect it to a file, whatever works). In theory it should also enable your fan control if disabled, and disable if it's enabled (like if you run it a second time). |
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Yeah, the dump of the second chip is just all FFs. Still, this is working surprisingly more than I expected of completely untested code. It finds the chips, their base addresses, and actually reads something that vaguely looks like some flash memory, since empty values are FF and not 00 like how it'd be with normal computer RAM. Plus it even has some sort of data at the beginning of the first chip. I think I'll compare to the original LHM code to see if I missed some step about enabling the second controller somehow. |
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@namazso same issue with a X570 AORUS MASTER. Has an ITE IT8688E and a ITE IT8792E for fan control. |
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Don't know if it helps, but here's some info from my system, too: |
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I did try to boot without HWinfo as startup, run the utility, but got the same outcome. |
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I see. It seems that whatever is going on, something is blocking access to the second superio. Something else you can do is run my python utility on a linux live usb and capture data that way. And if your motherboard has system 7 and system 8 pumps then it stands to reason that your system also has the third chip for those two headers. Another thing you could try I guess is a full shutdown and removal of power for 10 seconds or so then start back up again. |
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@cosmintnt LHM and therefore FanControl supports RAM temperature since a couple of months.
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@Blacktempel - Thanks for the headsup, I was doing it for so long with HWinfo plug in ... @TsunamiMommy: is there a way to chat somewhere about the topic? to avoid clutering the thread with relatively off-topic subject (like guiding me with Linux live usb, your script and trying to find what's not working). For sure we'll share possible findings in a more condensed way than replaying here back and forth. |
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@namazso Could you enable Discussions on this repository ? |
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Enabled. This repo wasn’t meant to be for end users originally which is why it was disabled. |
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untitled5 helped me,thank you. |
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based on some of the previous chatter about running this while GCC or FanControl was enabled, I decided to uninstall GCC, prevent FanControl from starting, rebooted, and then I ran your tool 3 consecutive times because I noticed the outputs changed between each run. I don't know if this provides more useful context. my 2nd chip still seems to only show FFs though attached in numbered order. |
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Yeah. The current utility for windows seems to be having trouble with setting up the window properly for reading the second superio. I'm working on seeing what can be done. As I've developed a tool based on this MR that does the same thing in linux, and it doesn't seem to have this problem. So there needs to be work done on a better windows utility to dump the memory contents. |
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Note on windows, the actual service that drove the fans in various MBs was EasyTuneEngineService for me, which can be installed even if you don't have GCC (e.g. SIV installed it for me). It's generally not the UI program like GCC or SIV that drives the fans, it's the service. I'd check if that's there, or maybe something renamed as they change the names of this stuff every few years. |
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The utility indeed had a bug, but it was only using the size of the first one for dumping the second superio, but that would only result in dumps where there is no first MMIO detected, causing empty dumps for the second one. However most of the logic doing the memory access is in the module, so should be alright. Especially since some people reported success. Anyway, I added Chip ID printout to the module, and made a new test program: Not sure how much it will help though |
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thanks for the updated tool. no luck with my 2nd chip, unfortunately I'm going to get a live Linux booted up and try the Python tool here in a minute |
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log.txt |
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I have a little bit of a side bar going with @TsunamiMommy in frankcrawford/it87#64 and we have made some progress on my 2nd chip... I think I will let them chime in with the full details when the time is right as I don't want to misrepresent anything. I will say, if you want to try to use scripts from that thread in a live boot Linux environment, be aware that you must disable Secure Boot for proper access to the hardware to be permitted. |
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Yeah it appears that ECIO and the standard ISA bridge access are not mutual. It appears that some boards use one method or the other but not both at the same time. This likely explains why some aren't getting access to the superio. |
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But then the question remains how would it have worked with the original WinRing0 implementation in LHM? it was doing pretty much exactly the same as what I did here. |
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Oh, actually that's simple to explain: ECIO was added to LHM at some point, after I started porting a bunch of stuff over: LibreHardwareMonitor/LibreHardwareMonitor#1313 Yeah I guess that's a whole different thing to cover then |
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Yup. So it did help us figure it out. Because my gp utility can access ECIO if smfi isn't supported. And I saw valid data there. That's how I came to that conclusion. |
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Hey @namazso did you have a LHM branch going with this module? Otherwise I'll start implementing it. Seems to be pretty straight forward compared to the old implementation, but I wouldn't mind a few guidelines if there is any gotchas. Like which MMIOState to use in which case. The "original" for the old "restore" method that's obvious, but the other ones I'm not so sure. |
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I don’t have any, so feel free to! You’ll probably want to revert the file deletion from my original PR, and use the module from here for the ISA bridge version, and attempt just using the LpcIO for the ECIO version. The later may need some extra work to be Dispose-correct. As for which MMIO state, you’d probably want to check if 4E is enabled already, and if not then just enable it. My implementation is mostly based on GCC’s so it may be somewhat different to the original LHM code. |
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Opened a LHM PR draft Need all the review I can get, just put the code in there but obv I couldn't test anything. Feedback/help welcomed. |
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Has anyone actually tested the bridge code on intel systems? |
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So, something that needs to be addressed with this code is that based on some testing and code verification I've done, intel systems cannot support two simultaneous windows. So that behavior will need to be changed. I've been working with a few linux users with intel systems and the behavior from this implementation (that I've mirrored in the it87 driver), only keep the last mmio address written to the |



Full, from-scratch Gigabyte EC module, completely untested. Provides full access to EC memory, so in theory could be used to write custom fan curves and whatnot.
Needs testing by someone who knows how to use a PawnIO module, and actually owns some Gigabyte hardware, preferably both Intel and AMD.
Intended usage:
1. Load module
This will just do Intel/AMD detection and that's all.
2. ioctl_find_superio_mmio
Performs 2E/2F and 4E/4F chip detection, if a supported chip is found retrieves MMIO base address.
3. ioctl_iomem_mmio_set_state
Enable MMIO mapping on ISA bridge. Intel can have both while AMD can only have one, unless I misunderstood how it works.
4. ioctl_map_superio_mmio
Actually map the range to (kernel-mode) virtual memory.
5. ioctl_access_superio_mmio
Read/Write/Modify values in the mapped MMIO range.
6. Unload
Unload will unmap mapped regions and restore ISA bridge config.