Try and migrate the old GigabyteController stuff with PawnIO#2014
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* Bring back WinRing0 era GigabyteController stuff * ISABridge use the PawnIO module with its built-in logic * Ecio uses LpcIO directly (not sure about the initialization logic in TryCreate() to make this work)
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I have a Gigabyte board that doesn't work with the current LHM. I can test it for you if you want. |
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Pull Request Overview
This PR adds support for a Gigabyte controller present on some motherboards that uses memory-mapped I/O via the ISA Bridge to control the 2nd ITE EC. The changes introduce new classes to detect and manage this controller, with fallback logic for ECIO port-based controllers on AMD systems.
- Adds
IsaBridgeGigabyteControllerandEcioPortGigabyteControllerimplementations - Extends
IGigabyteControllerinterface withIDisposablefor proper resource cleanup - Integrates detection logic into
LpcIOto automatically find and use the appropriate controller
Reviewed Changes
Copilot reviewed 8 out of 9 changed files in this pull request and generated 8 comments.
Show a summary per file
| File | Description |
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| LibreHardwareMonitorLib/Resources/PawnIo/IsaBridgeEC.bin | Binary resource for PawnIO driver module supporting ISA Bridge EC operations |
| LibreHardwareMonitorLib/PawnIo/IsaBridgeEc.cs | Wrapper class for ISA Bridge EC operations including state management |
| LibreHardwareMonitorLib/LibreHardwareMonitorLib.csproj | Adds IsaBridgeEC.bin as embedded resource |
| LibreHardwareMonitorLib/Hardware/Motherboard/Lpc/LpcIO.cs | Integrates Gigabyte controller detection and vendor detection logic |
| LibreHardwareMonitorLib/Hardware/Motherboard/Lpc/IsaBridgeGigabyteController.cs | Controller implementation using ISA Bridge MMIO for fan control |
| LibreHardwareMonitorLib/Hardware/Motherboard/Lpc/IT87XX.cs | Updates Close() method to dispose of Gigabyte controller |
| LibreHardwareMonitorLib/Hardware/Motherboard/Lpc/IT879xEcioPort.cs | Low-level port communication class for IT879x EC I/O operations |
| LibreHardwareMonitorLib/Hardware/Motherboard/Lpc/IGigabyteController.cs | Extends interface with IDisposable |
| LibreHardwareMonitorLib/Hardware/Motherboard/Lpc/EcioPortGigabyteController.cs | Alternative controller implementation using ECIO ports for AMD systems |
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If anyone wants to test it: logged in to GitHub: not logged in to GitHub: https://nightly.link/LibreHardwareMonitor/LibreHardwareMonitor/actions/runs/19089693441/LibreHardwareMonitor.zip |
* Fix inverted logic * Remove IsaBridgeEc field init * Format document
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I have tried the last build of the library. I'm seeing my RPM of my water pump. 
I tried to replace the |
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What we are looking for is if the control work on those secondary ITE chips. |
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The ISA bridge impl here will just enable the address translation. You still need to perform the write to the fan disable byte, similar to how the old implementation did, except with the ioctls. For reference, this was my "untitled5.exe" code: https://gist.github.com/namazso/8e25fc78f35a588e2b923fad5745c2cd Though you may want to look at the pre-PawnIO LHM implementation for actual implementing, I think I'm missing some version checks and whatnot. As for the ECIO stuff, I meant reusing the LpcPort instance you already have from LpcIO. That's why Dispose-correctness is important, because you don't want your parent LpcIO to dispose the Pawn module before GigabyteController is destroyed. |
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Is there a reason why when you set the MMIO state, if it's the index 0 you set 2E and when it's index 1 you set 4E? Not to sure I understand that logic. What about the "Both" option? Can I just set both all the time? Otherwise I gave it another go, as I understand much better what's going on. Used your gist for the "initialization" of the MMIO stuff, mapping, setting the state, then used the original LHM stuff for the actual FanControl byte in the mapped memory (offset 0x900 + 0x047). Also reused the existing LpcPort of the ITE chip when doing creating the ECIO stuff. |
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I'll test the new code tonight or tomorrow. |
Yes, the first superio chip is on port 2E/2F while the second is on 4E/4F. For the fan disable thing you only want to care about the second chip, my implementation is just based on GCC and matches capabilities including support for first chip.
AMD supports only one translation at a time, so Both isn’t going to work there. You want to first check if the current / original state is 4E or Both, and only do any changes if it isn’t, to avoid conflicting GCC or others. I believe the original GCC code also did something like that. |
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Sorry to ask, but you keep mentioning GCC, I guess you mean Gigabyte Control Center? Is the source available somewhere or some reverse engineering work? So in my IsaBridgeEC.cs findmmio call, I should only return/care about the second chip if its available? TLDR:
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Thank you for the effort! The application either fails to start at all (net9 or net8)or or fails to access the controller (net472 or netstandard)Granted, I didn't have the time to doublecheck if I am doing the correct thing today yet. It might as well be an honest mistake on my end. Would appreciate if you tell what version I am supposed to grab for FanControl_245_net_8_0 to test properly, or I should to downgrade something. |
Yes.
It's reverse engineering.
Yeah. I don't know what the first chip does.
I'm not sure actually, but I think the behavior is the same across ECIO and ISA bridge, and in the ECIO code you seem to be disabling with writing 0? I think the original LHM code also was doing it like that. |
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Alright pushed some changes. I think this looks more like it. |
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The results with my board : 
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After a restart the missing headers were displayed in FanControl. But after another restart they all disappeared. 
I'll try to make them display again. |
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If it doesn't see the ITE chip itself, that's a problem before it even hits the new code I put in. |
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Ok, so I have tried some things and found a way to display the missing headers. If there is nothing connected to any of the fan headers it displays. Otherwise it doesn't. 
EDIT: After plugging back the fan header, the ITE chip seems to stay detected. I'll try rebooting multiple times. EDIT2: The ITE chip disappeared and won't show up after multiple reboot. |
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Here is the logs of yesterday night when the chip disappeared. It is quite underwhelming and I don't think this log file will help a lot : PawnIo_IsaBridgeEc_DebugLog.txt
The "hole" between 20h and 22h was all the restarts and doing the process described in my previous message. I also checked the FanControl general logs and linked the file at the time I restarted the app with the new version of the library |
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@Squadella the log I need is a different one named : PawnIo_IsaBridgeEc_DebugLog.txt |
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I provided it collapsed, I put it again here: |
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@Squadella Is that with the chip missing from lhm? As it's very clearly being detected in those logs. |
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I tried to upgrade FanControl around 21h. See this message Between 21h and 22h16 I restarted multiple times and no data was logged. At 22h16 I started FanControl with the previous version and it found the chip. |
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Pull Request Overview
Copilot reviewed 8 out of 9 changed files in this pull request and generated 12 comments.
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Check copilot things as well, my feedback was repeated below. |
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Thanks, now AMD Family 10 left and we're largely back to WinRing0 version :) |
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Thanks everyone! |
THIS IS A DRAFT/INTEGRATION ATTEMPT
I do not have access to a board to test, so this will need testers.
TEST PROTOCOL
Changes:
[NEED REVIEW] ISA Bridge
As per @namazso here, based the enable/disable on setting the MMIO_Enabled4E state.
[NEED REVIEW] For the ECIO stuff
For now did It87Enter -> FindBars() -> It87Exit as stated here
However not sure about the exit since there is a comment in IT87Exit which states
// Do not exit config mode for secondary super IO.