Thanks! I couldn't find MSR_CSTATE_CONFIG in the linked docs, but a search on GitHub resulted in various projects showing roughly what it can do, looks harmless enough to me.

For future reference, having the sorting and actual changes in separate commits would make it easier to review.

Fair point, a separate commit would have been better, indeed. Thanks for merging it. That register was mostly used for a workaround at some point (original Zen if I remember correctly).

Found a reference here (Revision Guide for AMD Family 17h Models 30h-3Fh Processors Publication # 56323 Revision: 1.01): https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/revision-guides/56323-PUB_1_01.pdf

1474 A Core May Hang After About 1044 Days
Description
A core will fail to exit CC6 after about 1044 days after the last system reset. The time of failure may vary
depending on the spread spectrum and REFCLK frequency.
Potential Effect on System
A core will hang.
Suggested Workaround
Either reboot system before the projected time of failure, or disable CC6 by
• programming MSRC001_0296[22] to 0b, and
• programming MSRC001_0296[14] to 0b, and
• programming MSRC001_0296[6] to 0b.
Fix Planned
No fix planned