AMD: Allow family 1Ah, add CPPC MSRs, support more codenames#29
Conversation
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Also want to ask about guidelines for editor config, e.g.
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Thanks, I’m away for a bit and will review this later. Regarding editor config, it’s probably a mess since there isn’t auto formatting for Pawn and a couple modules are contributions already. I personally do 4 spaces and max 120 chars per line, because that’s the width of the github preview on desktop and as such frequently used for a modern limit, so I prefer contributions in that format. |
Thanks @Erruar for testing
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@namazso I've verified these changes working with: AM4 system AM5 system APU Unfortunately my 240GE seems to have lost all PCI-E lanes and I can't boot to windows or use external VGA, so I'm unable to test RavenRidge desktop. What is left
Based on my code, these codenames use 32bit address, but I can't be sure this is 100% right. APU CPU I guess it would be fine to use whatever the table base address is returned by SMU with the exception of Thanks! |
KrackanPoint2 currently unknown
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Removing [WIP] tag, it seems to be working on the CPUs me and my users managed to test. Verified to work on Phoenix as well. |
source: https://github.com/torvalds/linux/blob/master/tools/arch/x86/include/asm/msr-index.h#L714
Needs testing. Also need to re-check Rembrandt model name as it differs from what I have in ZenStates, however I'm not completely sure - maybe both models are valid. Currently only KrackanPoin2 is not supported, but I'm almost sure it is using the same mailbox and interface versions as the rest of the more recent APUs.