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AMD: Allow family 1Ah, add CPPC MSRs, support more codenames#29

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namazso merged 5 commits into
namazso:mainfrom
irusanov:amd
Oct 9, 2025
Merged

AMD: Allow family 1Ah, add CPPC MSRs, support more codenames#29
namazso merged 5 commits into
namazso:mainfrom
irusanov:amd

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@irusanov

@irusanov irusanov commented Sep 24, 2025

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    CPU_Naples,
    CPU_FireFlight,
    CPU_Rome,
    CPU_Chagall,
    CPU_Lucienne,
    CPU_Phoenix,
    CPU_Phoenix2,
    CPU_Mendocino,
    CPU_Genoa,
    CPU_StormPeak,
    CPU_DragonRange,
    CPU_Mero,
    CPU_HawkPoint,
    CPU_StrixPoint,
    CPU_StrixHalo,
    CPU_KrackanPoint,
    CPU_KrackanPoint2,
    CPU_Turin,
    CPU_TurinD,
    CPU_Bergamo,
    CPU_ShimadaPeak
  • Fixes "transfer table to dram" command ID for RavenRidge (Zen/Zen+) class APUs

Needs testing. Also need to re-check Rembrandt model name as it differs from what I have in ZenStates, however I'm not completely sure - maybe both models are valid. Currently only KrackanPoin2 is not supported, but I'm almost sure it is using the same mailbox and interface versions as the rest of the more recent APUs.

@irusanov irusanov changed the title RyzenSMU: Allow family 1Ah (GraniteRidge for now) AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs Sep 25, 2025
@irusanov

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Also want to ask about guidelines for editor config, e.g.

  • max symbols on line (from the current code it seems you use ~100)
  • tabs (currently using 2 spaces for tab as that's what I'm used to and like for Javascript)

@namazso

namazso commented Sep 25, 2025

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Thanks, I’m away for a bit and will review this later.

Regarding editor config, it’s probably a mess since there isn’t auto formatting for Pawn and a couple modules are contributions already.

I personally do 4 spaces and max 120 chars per line, because that’s the width of the github preview on desktop and as such frequently used for a modern limit, so I prefer contributions in that format.

@irusanov irusanov changed the title AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs WIP: AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs Oct 1, 2025
@irusanov irusanov changed the title WIP: AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs WIP: AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs, support more codenames Oct 1, 2025
@irusanov irusanov changed the title WIP: AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs, support more codenames [WIP]: AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs, support more codenames Oct 1, 2025
@irusanov

irusanov commented Oct 8, 2025

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@namazso I've verified these changes working with:

AM4 system
Motherboard: MSI B550 Unify-X
CPUs: 1800X (SummitRidge), 1600AF (PinnacleRidge), 3600 (Matisse), 3900X (Matisse), 5300G (Cezanne), 5600X (Vermeer)

AM5 system
Motherboard: Asus Apex X870
CPUs: 9950X3D, 9600X, 9900X (GraniteRidge), Epyc 4124p, 7950X (Raphael)

APU
6800HS (Rembrandt)

Unfortunately my 240GE seems to have lost all PCI-E lanes and I can't boot to windows or use external VGA, so I'm unable to test RavenRidge desktop.

What is left

  • Fix the mapping of physical memory by choosing one of these two options:
  1. Remove the second base address from CPU class 3, like here: d4f1557
  2. Handle iomap based on the cpu class - introduce global g_class variable and mask g_table_base appropriately, thus rendering the high dword for RavenRidge and derivates obsolete.

Based on my code, these codenames use 32bit address, but I can't be sure this is 100% right.
Also when used with 32bit Windows, all CPUs use the low dword and there's a special command SetToolsDramAddress to set that address for use.

APU
RavenRidge, FireFlight, Dali, Picasso, Renoir, Lucienne, Cezanne, Mero, VanGogh

CPU
SummitRidge, Naples, Whitehaven, PinnacleRidge, Colfax, Matisse, CastlePeak, Rome, Vermeer, Chagall, Milan

I guess it would be fine to use whatever the table base address is returned by SMU with the exception of class 3.

Thanks!

@irusanov irusanov changed the title [WIP]: AMD: Allow family 1Ah (GraniteRidge for now), add CPPC MSRs, support more codenames [WIP]: AMD: Allow family 1Ah, add CPPC MSRs, support more codenames Oct 9, 2025
@irusanov irusanov changed the title [WIP]: AMD: Allow family 1Ah, add CPPC MSRs, support more codenames AMD: Allow family 1Ah, add CPPC MSRs, support more codenames Oct 9, 2025
@irusanov

irusanov commented Oct 9, 2025

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Removing [WIP] tag, it seems to be working on the CPUs me and my users managed to test. Verified to work on Phoenix as well.
Should be alright for a "first" version. The only outsdanding issue would be with the base address of class 3.

@namazso namazso merged commit f216654 into namazso:main Oct 9, 2025
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