[GlobalISel][AArch64] - Add G_UREM computeKnownBits#189087
[GlobalISel][AArch64] - Add G_UREM computeKnownBits#189087tejasgaikwad04 wants to merge 5 commits into
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-aarch64 Author: Tejas Gaikwad (tejasgaikwad04) ChangesAdd computeKnownBits support for G_UREM in GlobalISel. Progressing towards: #150515 Full diff: https://github.com/llvm/llvm-project/pull/189087.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 245ade77f736e..62c49bd8f581b 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,6 +285,36 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
+ case TargetOpcode::G_UREM: {
+ KnownBits LHSKnown(Known.getBitWidth());
+ KnownBits RHSKnown(Known.getBitWidth());
+
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
+ Depth + 1);
+
+ APInt MaxRHS = RHSKnown.getMaxValue();
+
+ if (MaxRHS.isPowerOf2()) {
+ unsigned LowBits = MaxRHS.logBase2();
+ // Upper bits are zero
+ Known.Zero.setBitsFrom(LowBits);
+ // Mask for lower bits
+ APInt Mask = APInt::getLowBitsSet(Known.getBitWidth(), LowBits);
+ // Propagate known bits from LHS for lower bits
+ Known.One |= (LHSKnown.One & Mask);
+ Known.Zero |= (LHSKnown.Zero & Mask);
+ break;
+ }
+ if (!MaxRHS.isZero()) {
+ unsigned LeadingZeros = MaxRHS.countLeadingZeros();
+ Known.Zero.setHighBits(LeadingZeros);
+ }
+
+ break;
+ }
+
case TargetOpcode::G_CONSTANT: {
Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());
break;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
new file mode 100644
index 0000000000000..f164d32a11bd3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem_aarch64_gisel_test.ll'
+ source_filename = "urem_aarch64_gisel_test.ll"
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+ target triple = "aarch64"
+
+ define i32 @urem_pow2(i32 %x) {
+ %y = urem i32 %x, 8
+ ret i32 %y
+ }
+...
+---
+name: urem_pow2
+
+body: |
+ bb.1 (%ir-block.0):
+
+ ; CHECK-LABEL: name: @urem_pow2
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29
+
+ liveins: $w0
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 8
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
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@davemgreen @RKSimon Can you please review |
🐧 Linux x64 Test Results
✅ The build succeeded and all tests passed. |
There was a problem hiding this comment.
I think you can avoid this intermediate Mask APInt.
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Hi @arsenm , I’ve updated the branch with the latest base changes. Thanks! |
You can test this locally with the following command:git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp --diff_from_common_commit
View the diff from clang-format here.diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 9756db713..331c80ac7 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,7 +285,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
- //support for G_UREM
+ // support for G_UREM
case TargetOpcode::G_UREM: {
KnownBits LHSKnown(Known.getBitWidth());
KnownBits RHSKnown(Known.getBitWidth());
|
| case TargetOpcode::G_UREM: { | ||
| KnownBits LHSKnown(Known.getBitWidth()); | ||
| KnownBits RHSKnown(Known.getBitWidth()); | ||
|
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There was a problem hiding this comment.
This shouldn't reimplement all of this logic; it's all implemented in KnownBits::urem already.
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Apologies for Creating a new PR, https://github.com/llvm/llvm-project/pull/193455/changes , closing this PR. |
This updates the implementation of G_UREM in GlobalISel to use KnownBits::urem instead of reimplementing the logic. Supersedes #189087.
This updates the implementation of G_UREM in GlobalISel to use KnownBits::urem instead of reimplementing the logic. Supersedes llvm#189087.
This updates the implementation of G_UREM in GlobalISel to use KnownBits::urem instead of reimplementing the logic. Supersedes llvm#189087.
Add computeKnownBits support for G_UREM in GlobalISel.
Handles power-of-two RHS precisely and conservatively bounds results otherwise.
Includes an AArch64 MIR test using gisel-value-tracking.
Progressing towards: #150515