diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index f0b455fbdc7d0..9756db713ffdd 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -285,6 +285,37 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known, } break; } + //support for G_UREM + case TargetOpcode::G_UREM: { + KnownBits LHSKnown(Known.getBitWidth()); + KnownBits RHSKnown(Known.getBitWidth()); + + computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts, + Depth + 1); + computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts, + Depth + 1); + + APInt MaxRHS = RHSKnown.getMaxValue(); + + if (MaxRHS.isPowerOf2()) { + unsigned LowBits = MaxRHS.logBase2(); + // Upper bits are zero + Known.Zero.setBitsFrom(LowBits); + // Mask for lower bits + KnownBits TruncLHS = LHSKnown.trunc(LowBits).zext(Known.getBitWidth()); + + Known.One |= TruncLHS.One; + Known.Zero |= TruncLHS.Zero; + break; + } + if (!MaxRHS.isZero()) { + unsigned LeadingZeros = MaxRHS.countLeadingZeros(); + Known.Zero.setHighBits(LeadingZeros); + } + + break; + } + case TargetOpcode::G_CONSTANT: { Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue()); break; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir new file mode 100644 index 0000000000000..b5c70f46a35cc --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir @@ -0,0 +1,20 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple aarch64 -passes="print" %s -filetype=null 2>&1 | FileCheck %s + +name: urem_pow2 + +body: | + bb.1: + + ; CHECK-LABEL: name: @urem_pow2 + ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28 + ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29 + + liveins: $w0 + + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 8 + %2:_(s32) = G_UREM %0, %1 + $w0 = COPY %2(s32) + RET_ReallyLR implicit $w0