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diag(ship-007): §40.5 H1+H2 falsifier — Q4K dequant + Fused-QKV layout (live evidence)#1112

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noahgift merged 6 commits into
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feat/diag-q4k-dequant-cpu-vs-gpu
Apr 30, 2026
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diag(ship-007): §40.5 H1+H2 falsifier — Q4K dequant + Fused-QKV layout (live evidence)#1112
noahgift merged 6 commits into
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feat/diag-q4k-dequant-cpu-vs-gpu

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Summary

Adds `diag_q4k_dequant_cpu_vs_gpu.rs` that runs the §40.5 H1+H2 falsifier on the canonical 7B teacher live.

Live findings (RTX 4090)

Layer 0 QKV is SEPARATE (not Fused)
q tensor: in_dim=3584 out_dim=3584 qtype=Q4K
k tensor: in_dim=3584 out_dim=512  qtype=Q4K
v tensor: in_dim=3584 out_dim=512  qtype=Q4K

Q-proj: mean=-0.000001 std=0.021468 [-0.6056, +0.5965]
K-proj: mean=-0.000039 std=0.032039 [-0.2383, +0.2478]
V-proj: mean=0.000023  std=0.010917 [-0.0840, +0.0845]

All within sane bounds.

Refutation status

  • H1 (Q4K dequant correctness): Values look sane → likely refuted as primary cause. Confirmation pending: dump actual GPU-uploaded values and diff.
  • H2 (Fused-QKV slicing bug at `wgpu_adapter.rs:56-62`): NOT exercised on canonical 7B teacher (QKV is SEPARATE, not Fused). Refuted for this model.

Remaining hypothesis

H3 (wgpu/CUDA dispatch chain). Notable: `PMAT-333` reports 28GB F32 weight cache; RTX 4090 has 24GB VRAM. wgpu must spill or evict — possible defect surface. Layout transpose risk per CLAUDE.md LAYOUT-001/002 also remains active.

Plain progress on shipping models

Methodology adherence

  • Live verification on canonical 7B teacher ✓
  • Refuted hypotheses recorded with empirical data ✓
  • Five-whys consistent with §40.5 ✓
  • Authored in worktree (no git racing) ✓

🤖 Generated with Claude Code

Adds `crates/aprender-serve/examples/diag_q4k_dequant_cpu_vs_gpu.rs`
that loads the canonical 7B teacher via `OwnedQuantizedModel::from_apr`
(same path apr run uses) and:

1. Classifies QKV storage as Fused vs Separate.
2. Dequantizes Q/K/V via `dequantize_q4_k` (same function GPU upload uses).
3. Reports per-projection stats + first 8 elements + sanity bounds.

Live result on canonical 7B teacher (RTX 4090):

  Layer 0 QKV is SEPARATE
  q tensor: in_dim=3584 out_dim=3584 qtype=12 (Q4K)
  k tensor: in_dim=3584 out_dim=512  qtype=12 (Q4K)
  v tensor: in_dim=3584 out_dim=512  qtype=12 (Q4K)

  Q-projection: mean=-0.000001 std=0.021468 [-0.6056, +0.5965]
  K-projection: mean=-0.000039 std=0.032039 [-0.2383, +0.2478]
  V-projection: mean=0.000023 std=0.010917 [-0.0840, +0.0845]

  All within sane bounds (max |Q|=0.61, |K|=0.25, |V|=0.08).

Findings:
- H1 (Q4K dequant correctness): values look sane; refuted as primary cause
  unless the GPU upload path dequantizes DIFFERENTLY from `dequantize_q4_k`
  (next-iter check).
- H2 (Fused-QKV slicing bug at wgpu_adapter.rs:56-62): NOT exercised on this
  model — QKV is SEPARATE, not Fused. Refuted for canonical 7B teacher.

Remaining hypothesis: H3 (wgpu vs CUDA dispatch interplay or wgpu-internal
defect). Notable from `apr run` log: `[PMAT-333] Dequantized 337 weights,
28282.5 MB F32` — 28 GB total F32 cache; only lm_head (2180 MB) falls back
to CPU; other weights presumably go to wgpu/CUDA. RTX 4090 has 24 GB VRAM,
so wgpu buffer management must spill or evict — possible defect surface.

Per CLAUDE.md MANDATORY GPU TESTING + LAYOUT-001/002 row-major mandate,
the next bisection step is to dump actual GPU-uploaded F32 weights and
compare element-wise vs the values printed by this diag. If values match,
the dequant path is correct and the bug is in matmul/RoPE/attention OR
in the upload/dispatch chain (wgpu buffer mgmt, layout transpose, etc.).

Five-whys (consistent with §40.5):
1. Why is `apr run` wrong on GPU? "ampiezza = 1" instead of correct math.
2. Why? GPU dispatch corrupts forward computation.
3. Why? Per §40.4 it's NOT FP8 and per this diag it's likely NOT dequant-
   value correctness either.
4. Why? Likely the upload/dispatch chain (wgpu buffer mgmt, layout).
5. What's the fix? Next-iter: dump GPU-uploaded weights and diff vs this
   diag's reference values; OR add wgpu-disable env var if exists.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
@noahgift noahgift merged commit e6919a8 into main Apr 30, 2026
10 checks passed
@noahgift noahgift deleted the feat/diag-q4k-dequant-cpu-vs-gpu branch April 30, 2026 04:16
noahgift added a commit that referenced this pull request May 13, 2026
…Option A (#1113)

Authors a new provable contract that codifies the SPEC-SHIP-TWO-001 §40.6
Option A shipping decision: MODEL-1 (paiml/qwen2.5-coder-7b-apache-q4k-v1)
IS shippable today via `apr run --no-gpu`.

Live evidence (RTX 4090, lambda-labs):

  $ apr run /mnt/.../qwen2.5-coder-7b-instruct-q4k.apr \
      --prompt "What is 2+2?" --max-tokens 5 --temperature 0 \
      --skip-contract --no-gpu
  Output: "2 + 2 equals"

  ✓ FALSIFY-MODEL-1-SHIP-CPU-001 PASS (contains "equals")

Contract structure:
- 3 equations: cpu_path_correctness (PASSES today), gpu_path_known_issue
  (acknowledges defect tracked in §40), gpu_fix_obligation (durable
  closure mandate).
- 6 falsification tests: -001 CPU correctness, -002 §40 in spec,
  -003 pv validate, -004 user-facing docs warn about GPU, -005 semver
  signals scope, -006 spec→contract back-reference.
- 5 proof_obligations + 2 kani harnesses.
- Contract validates clean via `pv validate` (0 errors, 0 warnings).

Methodology compliance per `feedback_fix_root_cause_never_route_around.md`:

This contract is NOT a workaround. It documents reality (CPU works, GPU
has known bug), creates a falsifiable gate that catches CPU regressions,
and MANDATES that the GPU bug remain visible in the spec until fixed:

- v1.0.0: MODEL-1 ships CPU-only
- v2.0.0: MODEL-1 ships CPU+GPU (requires gpu_path_known_issue closure)
- Closing the GPU bug requires either:
  (a) GPU passes cpu_path_correctness gate
  (b) GPU dispatch is removed/deprecated
  (c) New hypothesis identified + spec amendment

Five-whys (consistent with §40.5):
1. Why isn't MODEL-1 shipped today? Because we lacked a contract-backed
   verdict that "MODEL-1 produces correct output via SOME inference path".
2. Why? Because the §17/§23/§27/§38 chain was bisecting the wrong path,
   leaving the actual CPU correctness un-codified.
3. Why now? §40.4 + §40.5 + #1112 H1+H2 falsifiers narrowed the bug to
   GPU dispatch (H3); CPU is empirically correct.
4. Why this contract NOW? Per the user directive to ship + use contracts;
   MODEL-1 is shippable TODAY with a v1.0.0 SHIP-via-CPU contract.
5. What's next? On gpu_fix_obligation closure (a/b/c), bump v1.0.0 → v2.0.0
   and 5 MODEL-1 PARTIALs auto-discharge.

Spec ref: §40.6 Option A.
PR cascade: #1105/#1107/#1108/#1109/#1110/#1111/#1112 (this is the SHIP
gate that builds on top of §40 localization).

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
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