AMDGPU: Mark strict_fp16_to_fp as expand#177417
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Keep bf16/f16 values encoded as the low half of a 32-bit register, instead of promoting to float. This avoids unwanted FP effects from the fpext/fptrunc which should not be implied by just passing an argument. This also fixes ABI divergence between SelectionDAG and GlobalISel. I've wanted to make this change for ages, and failed the last few times. The main complication was the hack to return shader integer types in SGPRs, which now needs to inspect the underlying IR type.
This prevents a regression in a future change.
This was referenced Jan 22, 2026
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This was referenced Jan 22, 2026
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis prevents a regression in a future change. Full diff: https://github.com/llvm/llvm-project/pull/177417.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index c5e720ce26bc0..d61eb9d11937b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -481,7 +481,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
MVT::v4i64, MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64},
Custom);
- setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
+ setOperationAction({ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP}, MVT::f64,
+ Expand);
setOperationAction(ISD::FP_TO_FP16, {MVT::f64, MVT::f32}, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
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@llvm/pr-subscribers-llvm-globalisel Author: Matt Arsenault (arsenm) ChangesThis prevents a regression in a future change. Full diff: https://github.com/llvm/llvm-project/pull/177417.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index c5e720ce26bc0..d61eb9d11937b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -481,7 +481,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
MVT::v4i64, MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64},
Custom);
- setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
+ setOperationAction({ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP}, MVT::f64,
+ Expand);
setOperationAction(ISD::FP_TO_FP16, {MVT::f64, MVT::f32}, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
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Base automatically changed from
users/arsenm/amdgpu/change-abi-16-bit-gfx6-gfx7
to
main
January 22, 2026 18:34
Harrish92
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to Harrish92/llvm-project
that referenced
this pull request
Jan 23, 2026
This prevents a regression in a future change.
Harrish92
pushed a commit
to Harrish92/llvm-project
that referenced
this pull request
Jan 24, 2026
This prevents a regression in a future change.
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This prevents a regression in a future change.