linear_int4_kernel for XPU#1130
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Reset to bfdbaf4 --------- Co-authored-by: mengfei25 <mengfei.li@Intel.com> Co-authored-by: LuFengqing <fengqing.lu@intel.com> Co-authored-by: Ratnam Parikh <114774508+ratnampa@users.noreply.github.com> Co-authored-by: Feng Yuan <feng1.yuan@intel.com>
mingfeima
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the biggest question should be why we need post op fusion here? does pytorch have it with cuda?
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@liangan1 CC |
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@sunjiweiswift for the perf benchmarking, please include other configs expect M=1. This would serve as a reference of final decision making. I expect that big M would have worse perf, but that's fine, we still need to know the numbers. |
#### Bugfix - [add lazy init for empty_xpu](#1115) - [nan propagation for soft_shrink](https://github.com/intel/torch-xpu-ops/pull/1116/files#diff-b7cb5876d000db957286c8b0e72badb2b7502402c8955334f1cc21c34c98a5b9) --------- Co-authored-by: Yu, Guangye <106960996+guangyey@users.noreply.github.com> Co-authored-by: ZhiweiYan-96 <zhiwei.yan@intel.com>
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| for (int i = 0; i < k; i += GroupK * Unroll) { | ||
| #pragma unroll | ||
| for (int iu = 0; iu < Unroll; iu++) { | ||
| uint8_t tmps8[TileK / 2]; |
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maybe we can do a little template trick to simply this piece of logic, have a template that handles all scernios and then pass corresponding args when called.
template <typename scalar_t, int SgSize, int TileK, int Unroll>
void tinygemm_kernel(...)
if (k % (SgSize * 32 * Unroll) == 0) {
// use tinygemm_kernel<...>
else {
// use tinygemm_kernel<...>
}
not a must to have, just a little trick.
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@xytintel not only this PR but the latest several CI all failed, could you check? |
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@EikanWang @liangan1 thoughts? |
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Pure SYCL path for. int4 gemm Benchmark results on PVC-1100. The remaining gaps are lack of usage of 2D load. | M | K | N | SrcT | WeiT | DstT | Bandwidth usage (BW usage) | |------------|-------------|-------------|----------|----------|----------|----------------| | 1 | 4096 | 4096 | float16 | float16 | float16 | 53.7% | | 1 | 4096 | 11008 | float16 | float16 | float16 | 57.4% | | 1 | 4096 | 16384 | float16 | float16 | float16 | 59.7% | | 1 | 12288 | 4096 | float16 | float16 | float16 | 77.3% | Besides PVC, the kernel can achieve 92.7% bandwidth usage on MTL 84.7% bandwidth usage on A750 --------- Co-authored-by: Yutao Xu <yutao.xu@intel.com> Co-authored-by: mengfei25 <mengfei.li@Intel.com> Co-authored-by: LuFengqing <fengqing.lu@intel.com> Co-authored-by: Ratnam Parikh <114774508+ratnampa@users.noreply.github.com> Co-authored-by: Feng Yuan <feng1.yuan@intel.com> Co-authored-by: Yu, Guangye <106960996+guangyey@users.noreply.github.com> Co-authored-by: ZhiweiYan-96 <zhiwei.yan@intel.com> Co-authored-by: Meng, Hengyu <hengyu.meng@intel.com>
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Pure SYCL path for. int4 gemm
Benchmark results on PVC-1100. The remaining gaps are lack of usage of 2D load.
Besides PVC, the kernel can achieve
92.7% bandwidth usage on MTL
84.7% bandwidth usage on A750