This test chip was put together by the Zedulo Tech team and @egorxe . It was taped out on the wafer.space Run-1 using open source PDK GF180MCU technology. The main goal for this tapeout was to test the flow and several open-source IPs.

IPs present on chip:

1. Caravel test harness port.
2. Zedulo UART2GPI IP.
3. Several blocks of eFuse memory generated with the gf180mcu eFuse compiler.
4. SPI-controlled SRAM memory.

This project is based on the Caravel project template for wafer.space. Caravel VexRiscv CPU core is mostly used to control the Wishbone bus connected to the eFuse blocks. For more info on the Caravel, please check the template repository and the original Caravel documentation.

Caravel CPU address map:

Three variations of eFuse blocks are present on this chip:

1. Synchronous eFuse memory with Wishbone interface connected to the Caravel core. Four blocks of different sizes: 1024x32, 128x8, 32x8, 64x32 (ip/efuse_wb_mem_*).
2. Synchronous eFuse memory with SPI interface connected to the external pads. (ip/efuse_spi_mem_256x8). Supported SPI protocol is a subset of the common SPI EEPROM protocol used, for example, in 25-series EEPROM devices.
3. Asynchronous eFuse memory, which is read and latched once on reset (ip/efuse_async_mem_1x8). Five blocks are present, four of them are mapped to the Caravel Wishbone as a single 32-bit memory word, and the interface of the remaining one is mapped to the external pads.

For more info on eFuse, please check the documentation in the eFuse compiler repository.

The UART2GPI IP is an UART-to-peripheral bridge that provides control of multiple IP blocks through a simple serial interface. The UART2GPI consists of the following IP blocks: UART, GPIO, PWM, and I2C IP. All IPs are based on OpenTitan IP cores with 32-bit register interfaces compatible with OpenTitan register conventions.

The UART2GPI uses a 6-byte command protocol:

Each IP can be selected using its respective code:

The UART2GPI connects to the following chip pads (see Chip pinout table for details). For detailed information on IP register configuration and usage, refer to the https://opentitan.org/book/hw/ip/.

TODO

This repository contains a Nix flake that provides a shell with the leo/gf180mcu branch of LibreLane.

Simply run nix-shell in the root of this repository.

With this shell enabled, run the implementation, first implementing the Caravel core (can be skipped as all required files are already in the repository):

make caravel-librelane

After Caravel implementation is done, run the implementation of the chip top:

make librelane

To run everything at once:

make all

For more info, please see the original gf180mcu-project-template and check the GitHub CI scripts in this repository.

Verification is based on the cocotb using Icarus Verilog as the default simulator and extending the gf180mcu-caravel-template testbench. To run all the provided tests on behavioral RTL, please run:

make sim

To run all the tests on the post-implementation gate-level netlist (will be present in the final folder after implementation), run:

make sim-gl

Cocotb testbench is located in cocotb/chip_top_tb.py and can be run either directly with Python or via pytest. Makefile targets launch all the tests via pytest with the number of parallel runs equivalent to the number of available CPU threads. The list of available tests can be found in cocotb/test_list.json. Each test has a dictionary associated with it, allowing to pass additional parameters to the cocotb test if needed.

For example, to run the uart2gpi test with python, cd to the cocotb dir and launch:

TEST=uart2gpi python3 chip_top_tb.py

The same with pytest (easier test management, but no real-time testbench output to the terminal):

pytest --test=uart2gpi chip_top_tb.py

Caravel-based tests (with names starting with caravel_) consist of a Verilog testbench (caravel/sim/caravel_tb) and a Caravel program (caravel/sim/caravel_sw), with the cocotb testbench acting mostly as a test framework. Tests for the async eFuse, SPI SRAM & eFuse and the UART2GPI do not use the Caravel infrastructure and are written entirely in Python.

Test list:

Pad numbering in the table starts from the lower left (with the default GDS orientation) and proceeds counterclockwise. Numbering should be compatible with the wafer.space COB project.