Project template for wafer.space MPW runs using the gf180mcu PDK.

Too manage all dependencies, the project template includes a Nix shell with all the required tools. Install Nix and LibreLane by following the Nix-based installation instructions: https://librelane.readthedocs.io/en/latest/installation/nix_installation/index.html To activate the shell, simply run nix-shell in the root directory of this repository. The subsequent steps assume that you are in the Nix shell of the project template.

The project template uses the open_pdks gf180mcuD variant of the PDK. To clone the latest PDK version via Ciel, run make clone-pdk.

With the Nix shell enabled, run the implementation:

make librelane

You can find all output artifacts in the librelane/runs/<timestamp>/ directory.

After completion, you can view the design using the OpenROAD GUI:

make librelane-openroad

Or using KLayout:

make librelane-klayout

For the verification of the chip we use cocotb. Cocotb is a Python-based testbench environment. The simulator that is used by the project template is Icarus Verilog.

The testbench is located in cocotb/chip_top_tb.py. To run the RTL simulation, run the following command:

make sim

To run the GL (gate-level) simulation, run the following command:

make sim-gl

In both cases, a waveform file will be generated under cocotb/sim_build/chip_top.fst. You can view it using a waveform viewer, for example, GTKWave.

make sim-view

You can now update the testbench according to your design.

The source files for this template can be found in the src/ directory. chip_top.sv defines the top-level ports and instantiates chip_core, chip ID (QR code) and the wafer.space logo. To allow for the default bonding setup, do not change the number of pads in order to keep the original bondpad positions. To be compatible with the default breakout PCB, do not change any of the power or ground pads. However, you can change the type of the signal pads, e.g. to bidirectional, input-only or e.g. analog pads. The template provides the NUM_INPUT and NUM_BIDIR parameters for this purpose.

The actual pad positions are defined in the LibreLane configuration file under librelane/config.yaml. The variables PAD_SOUTH/PAD_EAST/PAD_NORTH/PAD_WEST determine the respective pad placement. The LibreLane configuration also allows you to customize the flow (enable or disable steps), specify the source files, set various variables for the steps, and instantiate macros. For more information about the configuration, please refer to the LibreLane documentation: https://librelane.readthedocs.io/en/latest/

To implement your own design, simply edit chip_core.sv. The chip_core module receives the clock and reset, as well as the signals from the pads defined in chip_top. As an example, a 42-bit wide counter is implemented.

The template supports the following slot sizes: 1x1, 0p5x1, 1x0p5, 0p5x0p5. By default, the design is implemented using the 1x1 slot definition.

To select a different slot size, simply set the SLOT environment variable. This can be done when invoking a make target:

SLOT=0p5x0p5 make librelane

Alternatively, you can export the slot size:

export SLOT=0p5x0p5

You can change the slot that is selected by default in the Makefile by editing the value of DEFAULT_SLOT.

The project template has support for selecting libraries with the below environment variables:

For example, to build the 0p5x0p5 chip with 3v3 libraries:

SLOT=0p5x0p5 SCL=gf180mcu_as_sc_mcu7t3v3 PAD=gf180mcu_ocd_io SRAM=gf180mcu_ocd_ip_sram make librelane

The default values can be changed in the Makefile.

To build just the padring without any standard cell rows, digital routing or filler cells, run the following command:

make librelane-padring

It is also possible to build the padring for other slot sizes:

SLOT=0p5x0p5 make librelane-padring

To check whether your design is suitable for manufacturing, run the gf180mcu-precheck with your layout.