This repository contains an eFuse compiler for the GF180MCU technology. Original compiler was used to do a tapeout during the Open MPW GFMPW-0 run, but after that, the compiler was rewritten from scratch to increase density and automate the flow. The current version of the compiler is much more usable, but still not verified in silicon, and should be treated as experimental. The first test chip with eFuse generated by the current compiler was taped out on wafer.space Run 1, and test results are expected in summer 2026.

eFuse compiler provides:

• Generation of synchronous or asynchronous nonvolatile eFuse memory array for the GF180MCU process with open source PDK.
• GDS and other files necessary for integration into any GF180MCU-based chip design.
• Configurable word width and memory depth.
• Automatic DRC/LVS verification and analog simulation of the generated array in Xyce.
• Synchronous eFuse memory density up to 10 kbits/mm^2 (without a digital wrapper).
• Digital wrappers generation providing Wishbone or SPI interface to eFuse memory.

The quickest way to run the compiler is to have a LibreLane-compatible Nix installed, clone the compiler and the PDK repositories, and run the compiler from the nix shell. You can achieve that with the following command sequence:

git clone https://github.com/egorxe/gf180_efuse_compiler
cd gf180_efuse_compiler
git clone https://github.com/wafer-space/gf180mcu
nix-shell
./efuse.py 16 1 --digital-wrapper=wishbone

For more info on compiler arguments, environment requirements, and IP integration, please refer to the documentation.

Output files for several precompiled configurations are provided in the releases. Here are some GDS screenshots.

Minimal synchronous eFuse array with 16 1-bit words.

128x8 eFuse array with SPI digital wrapper built out of 4 64x8 blocks.