Quick Presets

Layer Assignment (8 Signal + 4 GND + 2 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 SIG
L9 GND
L10 SIG
L11 PWR
L12 SIG
L13 GND
L14 SIG

Copper Layers (14)

Prepreg Layers (7)

Core Layers (6)

Total Board Thickness
2.400mm
2400 ยตm
vs 2.4mm
+0 ยตm
Copper (14L)
490 ยตm
Prepreg (7L)
983 ยตm
Core (6L)
1000 ยตm

Stackup Visualization

L1 – Top SignalSIG 35ยตm
PP1 114ยตm
L2 – GNDGND 35ยตm
Core 1 100ยตm
L3 – SignalSIG 35ยตm
PP2 114ยตm
L4 – PWRPWR 35ยตm
Core 2 200ยตm
L5 – SignalSIG 35ยตm
PP3 114ยตm
L6 – GNDGND 35ยตm
Core 3 200ยตm
L7 – SignalSIG 35ยตm
PP4 (Center) 185ยตm
L8 – SignalSIG 35ยตm
Core 4 200ยตm
L9 – GNDGND 35ยตm
PP5 114ยตm
L10 – SignalSIG 35ยตm
Core 5 200ยตm
L11 – PWRPWR 35ยตm
PP6 114ยตm
L12 – SignalSIG 35ยตm
Core 6 100ยตm
L13 – GNDGND 35ยตm
PP7 114ยตm
L14 – Bottom SignalSIG 35ยตm
SOLDER MASK (BOTTOM)
Outer Signal
Inner Signal
GND Plane
PWR Plane
Prepreg
Core
๐Ÿ’ก Common 14-Layer Targets
2.0mm: High-density HDI/BGA breakout
2.4mm: Standard 14L (most common)
2.8-3.2mm: Server, networking, AI accelerators
3.5mm+: Backplanes, heavy copper designs
๐Ÿ“ Impedance Reference
Microstrip: L1โ†’L2, L14โ†’L13
Stripline: L3, L5, L7, L8, L10, L12
Dual-stripline: L7โ†”L8 center pair
โšก 14-Layer Design Strategy
8 Signal Layers: L1, L3, L5, L7, L8, L10, L12, L14 โ€” Maximum routing density for complex BGA fanout and high-speed interfaces.
4 GND Planes: L2, L6, L9, L13 โ€” Distributed ground reference at regular intervals minimizes return path lengths.
2 PWR Planes: L4, L11 โ€” Symmetric power distribution; add splits for multiple voltage domains.
Center Pair: L7-L8 share PP4 โ€” ideal for broadside-coupled differential pairs or high-speed memory routing.
Symmetry: Structure is symmetric about PP4 center for optimal thermal expansion and warpage control.