Keep up to datewith all the newsabout Tristan Project Introducing the European Unified RISC-V IP Access Platform (UAP)January 28, 2026 Using a Performance Model to Implement a Superscalar CVA6November 4, 2025 Support for upstream UVM 2017 in VerilatorNovember 3, 2025 Extending RISC-V with SCAIE-V: Portable, Efficient, and Scalable Custom Instruction IntegrationOctober 30, 2025 Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class CoresSeptember 22, 2025 From guesswork to guidance: Mastering processor co-design with Codasip Exploration FrameworkSeptember 15, 2025 Enhancing RTL coverage reporting in Verilator with new features and computation optimizationsAugust 30, 2025 Strengthening European Sovereignty through Open HW: Insights from the RISC-V Summit EuropeMay 21, 2025 Join Us for the EDGE AI Academy Summer School in Pisa – July 7–8, 2025!May 20, 2025 Enabling complex HDL co-simulation scenarios using Renode’s Direct Programming Interface supportApril 30, 2025 TRISTAN EDA Tool training at RISC-V Summit Europe 2024November 25, 2024 Trace-based evaluation of CPU cache usage in RenodeOctober 1, 2024 Technical Conference 2024September 15, 2024 TRISTAN Technical Conference 2024 AnnouncedJuly 20, 2024 TRISTAN at RISC-V Summit Europe 2024June 7, 2024 TRISTAN Initial requirements and feedback for processor and hardware IPsNovember 10, 2023
