How to ensure the right data arrives at a shared memory at the right time.
The number of processes running simultaneously inside of chips is growing, fueled by massive increases in data from AI and sensors everywhere. The challenge now, particularly in multi-die assemblies, is how to prioritize where signals go, how quickly they move, and when they’re supposed to arrive at shared memories. Andy Nightingale, vice president of product management and marketing at Arteris, explains how to manage quality of service for various IP blocks inside a multi-die chip, the impact of coherent versus non-coherent approaches, and what’s needed to scale up and scale out a design.
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