Blog
Verilator Gap Checker: Automatically Detecting Feature Gaps in Verilator with AI
The Problem Verilator is the fastest open-source SystemVerilog simulator — 10–100× faster than commercial tools in many scenarios. But it has a...
Linux on CVA6 on Agilex7 development kit
Today, we are going to talk about the work we did with our friends from Thales in order to support CVA6 on an Agilex7 development kit...
Enabling UVM Support in Verilator Series — Constrained Randomization Support for Structs
In our last blog, we described how we implemented constrained randomization support for various array types in Verilator. Building on that, we’ve...
Enabling UVM Support in Verilator Series — Constrained Randomization Support for All Types of Arrays
The DI-OSVISE project (De:sign Initiative - Open Source Verification of RISC-V Instruction Set Extensions), funded by the BMBF, aims to advance...
SoC Integration using Amaranth HDL
In this post, we will explore the challenges of building an SoC using Amaranth HDL to create the top-level design and integrate pre-existing...
Delving into ITP and HOL4 for digital design and verification
I came across this very interesting paper from Andreas Lööw, A Proof-Producing Translator for Verilog Development in HOL, and that piqued my...
Enabling UVM Support in Verilator Series — Basic Randomization Support for Aggregate data types
Randomness Unleashed: Basic Randomization in Verilator In a previous blog post, If-Else Constraint Support, we dove into the importance of...
Enabling UVM Support in Verilator Series — Our CI System and Test Models
A primary objective of OSVISE is to foster innovation, and PlanV as a part of this initiative, is working to bridge the gap between open-source...
OSVISE : Verilator Series –Enabling UVM Support— Part 1: If-Else Constraint Support
PlanV: Enabling UVM Support in Verilator for RISC-V Verification PlanV is a two-year-old startup in the RISC-V domain based in Munich. This blog...
OSVISE : Verilator Series – Monitor issue fix in Verilator
DI-OSVISE (De:sign Initiative - Open Source Verification von RISC-V Instruktionssatzerweiterungen) is a project sponsored by BMBF to foster the...