./cad/py-PyRTL, Register-transfer-level hardware design and simulation

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]


Branch: CURRENT, Version: 0.12nb1, Package name: py313-PyRTL-0.12nb1, Maintainer: ryoon

PyRTL provides a collection of classes for pythonic register-transfer
level design, simulation, tracing, and testing suitable for teaching
and research. Simplicity, usability, clarity, and extensibility
rather than performance or optimization is the overarching goal.


Required to run:
[lang/py-six] [lang/python310]

Master sites:

Filesize: 514.657 KB

Version history: (Expand)


CVS history: (Expand)


   2025-12-27 17:31:09 by Ryo ONODERA | Files touched by this commit (3)
Log message:
cad/py-PyRTL: Fix the error from render_trace() on Jupyter

* Do not fail with 'Javascript Error: $ is not defined'.
* Bump PKGREVISION.
   2025-08-03 17:39:41 by Ryo ONODERA | Files touched by this commit (3)
Log message:
cad/py-PyRTL: Update to 0.12

Changelog:
0.12 - 2025-07-28
Added

    GateGraph is an alternative PyRTL logic representation, designed to simplify \ 
analysis.

Changed

    Rewrote output_to_verilog and output_verilog_testbench. The new \ 
implementation's output should be much easier to read:
        Single-use expressions are inlined.
        Try mangling unusable WireVector and MemBlock names first, before \ 
assigning them entirely new names.
        Add comments to the generated Verilog that show the un-mangled names.
    Many documentation improvements:
        Most methods and functions now have examples.
        Consistently use canonical top-level pyrtl.* names, rather than \ 
module-level names (pyrtl.WireVector, not pyrtl.wire.WireVector).
        Enabled intersphinx for clickable standard library references (list, \ 
dict, etc).
        Set up doctest for examples, to verify that documentation examples still \ 
work.
    Switched from pylint and pycodestyle to ruff:
        Applied many ruff fixes.
        Reformatted the code with ruff format.
        Updated tox to run ruff check and ruff format.

Removed

    Removed remaining Python 2 support.

Fixed

    Fixed XOR implementation in and_inverter_synth pass (@EdwinChang24)
    output_verilog_testbench should not re-initialize RomBlocks.
    FastSimulation was not setting init_memvalue correctly (renamed to \ 
SimulationTrace.memory_value_map).
    Specify bitwidths for Verilog initial register and memory values. They were \ 
previously unsized constants, which are implicitly 32-bit signed, which could \ 
cause surprises.
   2025-06-14 07:49:50 by Ryo ONODERA | Files touched by this commit (2)
Log message:
cad/py-PyRTL: Update to 0.11.3

Changelog:
## [0.11.3] - 2025-06-12

### Added

- An optimization pass to [optimize inverter \ 
chains](https://github.com/UCSBarchlab/PyRTL/blob/d5f8dbe53f54e61e1d54722449e4894b885243c7/pyrtl/passes.py#L130)
- `one_hot_to_binary` encoder \ 
([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.helperfuncs.one_hot_to_binary))
- `binary_to_one_hot` decoder \ 
([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.helperfuncs.binary_to_one_hot))

### Changed

- More support for signed integers: Signed integers can now be used in `RomBlock`'s
  `romdata`, `Simulation`'s `mem_value_map`, and Verilog-style register reset values.
- Improved documentation:
  - \ 
[conditional_assignment](https://pyrtl.readthedocs.io/en/latest/basic.html#module-pyrtl.conditional)
  - [WireVector \ 
equality](https://pyrtl.readthedocs.io/en/latest/basic.html#wirevector-equality)

### Fixed

- Use iteration instead of recursion to avoid stack overflow in `find_producer`.
   2024-10-17 11:28:08 by Thomas Klausner | Files touched by this commit (1)
Log message:
py-PyRTL: remove unused test dependencies
   2024-09-18 08:23:15 by Thomas Klausner | Files touched by this commit (1)
Log message:
py-PyRTL: add missing tool dependency

Fix testing and add test status.
   2024-08-10 04:32:59 by Ryo ONODERA | Files touched by this commit (2)
Log message:
cad/py-PyRTL: Update to 0.11.2

Changelog:
### Added

- Added an `initialize_registers` option to `output_to_verilog`
  documentation

### Changed

- Improved handling of signed integers.

### Fixed

- Fixed a `wire_matrix` bug involving single-element matrices of `Inputs` or \ 
`Registers`.
   2024-06-05 19:16:08 by Ryo ONODERA | Files touched by this commit (3)
Log message:
cad/py-PyRTL: Update to 0.11.1

Changelog:
0.11.1:
Upgrade download-artifact action to v4, for compatibility with upload

-artifact v4.

0.11.0:
Set PyRTL's Python package version from `git tag`.

This avoid keeping the latest version number in two places, `pyproject.toml`
and `git tag`. Simplify instructions in release/README.md.

Rename some GitHub workflow jobs to clarify their purpose.

0.11.0rc1:
GitHub actions to automate PyRTL releases to TestPyPI and PyPI.

- Migrade from `setup.{py,cfg}` to `pyproject.toml`
- Add `python-release.yml` workflow
- Prepare a `0.11.0rc1` release.
- Rename `python-package.yml` to `python-test.yml` and upgrade checkout action \ 
to `v4`.
- Add release documentation at `release/README.md`
- Use latest python and ubuntu versions for readthedocs.
- Remove the release version number from the sphinx configuration
  (`docs/conf.py`). It doesn't seem to do anything.
   2023-01-24 15:32:20 by Ryo ONODERA | Files touched by this commit (3)
Log message:
py-PyRTL: Update to 0.10.2

Changelog:
* Fix tox tests on Apple M1, aarch64.
* Fix another tox tests.
* Fix error message typo.
* Support newer graphviz to generate SVG.
* Fix constant propagation for synthesized blocks.
* Improve net_connections() function.
* Improve paths() function.
* Update documentation.