MIPS ARC-V Processor IP

MIPS ARC-V Processor IP™ is based on the open standard RISC-V instruction set architecture (ISA), extending the current ARC portfolio and giving customers access to the growing RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.

To accelerate software development, the ARC-V processors are supported by the trusted MIPS MetaWare Development Toolkit. In addition, MIPS’ extensive portfolio of EDA tools provide an out-of-the-box development and verification environment to help design and fully verify RISC-V-based SoCs.

Key Benefits

Power & Area Efficient

Achieve maximum performance with minimum power & area consumption

Configurable

Optimize PPA of each processor instance

Extensible Instruction Set

Make application-specific customizations

Broad Ecosystem

Achieve faster time to market

What's New

Enhancing RISC-V Embedded Processor Performance through Advanced Instruction Fusion

How the RISC-V ISA Offers Greater Design Freedom and Flexibility

Unlocking the Power of Instruction Fusion in ARC-V

ARC-V Processor IP Families

RMX Series

32-bit embedded processors optimized for ultra-low power

RHX Series

32-bit real-time processors with a high-speed, dual-issue 10-stage pipeline

RPX Series

64-bit host processors with SMP Linux and L2 cache support

"Lauterbach, the world's leading manufacturer of debug and trace tools and long-standing partner of MIPS, fully supports MIPS' RISC-V-based ARC-V™ Processor IP with its TRACE32 tools as a result of close collaboration between the companies' engineering teams. Lauterbach and MIPS are now continuing this close collaboration with joint customers to support them in optimizing and differentiating their chips and helping designers manage the complexity of today's SoCs."

"As the leading provider of system IP we see firsthand the increasing adoption of RISC-V processor IP by our customers, from automotive to consumer electronics to industrial applications. MIPS’ ARC-V™ Processor IP is a welcome addition to the RISC-V ecosystem, and we look forward to continued collaboration leveraging Arteris’ FlexNoC and Ncore network-on-chip IP to deliver optimized IP solutions and SoC connectivity to mutual customers."

"The breadth of the markets we serve requires our designers to have the flexibility to implement the most efficient processor for the job. As a user of MIPS ARC® Processor IP as well as RISC-V IP, among others, we think MIPS’ adoption of the RISC-V ISA is a good addition to the choices available in the RISC-V ecosystem."

"Our PX5 RTOS supports the increasingly popular RISC-V architecture, and we are pleased to see MIPS expand its processor portfolio to include RISC-V compatible processor IP. The PX5 RTOS offers fast and deterministic performance in a small memory footprint, and along with MIPS’ ARC-V™ Functional Safety Processors, can offer designers an efficient, reliable solution for their safety-critical, real-time systems."

"TASKING is proud to announce its support for MIPS’ ARC-V™ Processor IP. Our system-level verification and debugging tools are now available for use with ARC-V IP, whether simulated with the MIPS Virtualizer Development Kit or implemented in an FPGA or silicon. We are working closely with MIPS and their automotive customers to establish a trusted ecosystem for the development of systems that must meet functional safety and cybersecurity standards such as ISO 26262 and ISO 21434."

"As a manufacturer of debug tools, we see the growing importance of making software behavior visible in complex SoCs and the need for a powerful ecosystem to help companies accelerate their release cycles. As a long-standing partner of MIPS, PLS has a history of providing high-quality debug tools to MIPS ARC® processor customers and will continue to support the new ARC-V™ Processor IP family with the PLS Universal Debug Engine."