Steven Herbst

get_value does not handle signed values properly

1

Just noticed that when `get_value` is used in conjunction with `SInt` types, the values are treated as unsigned. An example is shown below, where the value `214` is returned instead...

Looks like setting ``dump_waveforms=True`` for the ``ncsim`` target does not dump data types like arrays and structs, which can make it challenging to debug some kinds of hand-written designs and...

Unified time management in SystemVerilog / Verilator / SPICE / Verilog-AMS targets

1

The meaning of time flow between different kinds of simulation targets has diverged, and even within a given target there are some inconsistencies (e.g., some delays are in seconds, some...

These options are available for the SPICE target but not the VerilogAMS target. Adding these features would entail updates to **gen_amscf**, most likely in the lines of code that produce...

It would be nice if failures in an **expect** statement were formatted based on the signal type to aid debugging. In the example below, the **expect** statement triggers an exception,...

I'd suggest providing some feedback to the user if the signal they're trying to poke doesn't actually exist. The simple example below illustrates the issue and how it could potentially...

realtime monitoring of simulation output

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Hi, On my platform (macOS Sierra 10.12.5, vvp 11.0, iverilog 11.0) the display=True option of simulation.run doesn't provide realtime output when using the iverilog simulator. The simulation runs, but no...

Looks like the Vivado simulator outputs "x" when "x" is multiplied by "0". For that reason, we might want to have ``mul_real`` check for that condition and output "0" if...

At the moment, defining RANGE_ASSERTIONS will cause **svreal** to fail with a fatal error whenever a real value is outside of the range of the signal to which it is...