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Update instructions and add new ISA extensions#407

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flobernd merged 5 commits intomasterfrom
update-instructions
Dec 9, 2022
Merged

Update instructions and add new ISA extensions#407
flobernd merged 5 commits intomasterfrom
update-instructions

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@flobernd flobernd commented Nov 27, 2022 •
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Improve several instruction definitions

  • Change LDTILECFG and STTILECFG memory operand element type from INT32 to STRUCT
  • Require VEX.L=0 for JKZD/JKNZD
  • Set FCOMI isa-set for F{U}COMI{P}
  • Change MOV{H|L|LH|HL}P{S|D} register access from r to rw
  • Change MASKMOVDQU element types from INT32 to UINT8
  • Add implicit GS register operand to SWAPGS
  • Change RCPSS, ROUNDS{S|D}, SQRT{S|D} and RSQRTSS operand access from r to rw

Add new isa extensions

  • AMX-FP16
  • AVX-IFMA
  • AVX-NE-CONVERT
  • AVX-VNNI-INT8
  • RAO-INT
  • IPREFETCH
  • MSRLIST
  • WRMSRNS

@flobernd flobernd requested a review from athre0z November 27, 2022 20:06
@flobernd flobernd force-pushed the update-instructions branch from d787070 to 3cea091 Compare November 27, 2022 20:13
@flobernd flobernd marked this pull request as ready for review November 28, 2022 13:43
@athre0z athre0z added C-enhancement Category: Enhancement of existing features A-decoder Area: Decoder labels Dec 9, 2022
athre0z
athre0z approved these changes Dec 9, 2022
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LGTM!

@flobernd flobernd merged commit 8948d9a into master Dec 9, 2022
@flobernd flobernd deleted the update-instructions branch December 9, 2022 18:34
athre0z pushed a commit that referenced this pull request Feb 4, 2024
@flobernd @athre0z
Update instructions and add new ISA extensions (#407)
6c83141
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