[Mellanox] Configure buffer for queue 7 on T1 uplink ports in dual ToR scenario#115
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[Mellanox] Configure buffer for queue 7 on T1 uplink ports in dual ToR scenario#115
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Signed-off-by: Stephen Sun <stephens@nvidia.com>
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keboliu
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Jul 29, 2022
stephenxs
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Nov 24, 2023
…omatically (sonic-net#17188) #### Why I did it src/sonic-mgmt-common ``` * faa2a51 - (HEAD -> master, origin/master, origin/HEAD) Go Code format checker and formatter (#112) (8 hours ago) [faraazbrcm] * faaa9f5 - PathInfo optimizations (#115) (22 hours ago) [Sachin Holla] ``` #### How I did it #### How to verify it #### Description for the changelog
stephenxs
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Oct 20, 2025
…ically (sonic-net#24088) #### Why I did it src/sonic-dash-ha ``` * f36ffdd - (HEAD -> master, origin/master, origin/HEAD) Make deserializer more forgiven to parse dash_bfd_probe_state (#113) (6 hours ago) [yue-fred-gao] * 0a719f6 - Proper handling of entry not found in incoming vs decoding error (#114) (6 hours ago) [yue-fred-gao] * 2c589e7 - Unregister handlers after actor terminates (#115) (6 hours ago) [yue-fred-gao] * b39c778 - Add local nexthop ip (#116) (6 hours ago) [dypet] ``` #### How I did it #### How to verify it #### Description for the changelog
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Why I did it
Configure buffer for queue 7 on T1 uplink ports in dual ToR scenario
On uplink ports
DSCP 48=>TC 7=>queue 7Signed-off-by: Stephen Sun stephens@nvidia.com
How I did it
How to verify it
Which release branch to backport (provide reason below if selected)
Description for the changelog
Link to config_db schema for YANG module changes
A picture of a cute animal (not mandatory but encouraged)