[AMD] Optimize MiniMax-M2.5 - enable fused Triton kernel for FP8 KV cache write in aiter decode path#23620
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HaiShaw merged 1 commit intosgl-project:mainfrom Apr 25, 2026
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HaiShaw
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sogalin
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…l only The fused Triton kernel introduced in PR sgl-project#23620 (commit adc5932) is correct enough for non-speculative target-model decode (its original target, MiniMax-M2.5) but its bf16->fp8 implicit cast through tl.store does not match PyTorch .to(torch.float8_e4m3fn) bit-exactly. PyTorch casts with round-to-nearest-even + saturation; the Triton path on ROCm/HIP rounds differently and may not saturate, even when the per-tensor k_scale / v_scale are 1.0 (verified for Kimi-K2.5 Quark MXFP4 with kv_cache_dtype=fp8 by direct probe). Non-speculative inference tolerates this small numerical drift, but EAGLE3 draft decode reads back its own freshly written K/V cache on every subsequent draft step, so any drift in the draft cache compounds across draft steps and collapses the accept length: Kimi-K2.5-MXFP4 + EAGLE3 (8xMI300, in/out 8192/1024, conc 4): pr-23146 baseline : accept=3.26 out=675 tok/s + seqused_k fix (2bee3c3) : accept=3.46 out=706 tok/s + this commit (target-only gate): accept=3.97 out=807 tok/s pr-23461 baseline reference : accept=3.97 out=798 tok/s Restrict the fast path to target-model backends by checking model_runner.is_draft_worker. The SWA path is unchanged (it already works because SWA models did not exercise the corrupted draft cache). The Triton kernel itself can be revisited later to match PyTorch fp8 cast semantics; until then, draft model writes route through the legacy MHATokenToKVPool.set_kv_buffer path.
vguduruTT
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May 2, 2026
…ache write in aiter decode path (sgl-project#23620)
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Motivation
--kv-cache-dtype fp8_e4m3) and unifiedattention enabled, the decode KV cache write previously required two
separate kernel launches: a bf16→fp8 dtype cast (
float8_copy_kernel)followed by a paged store (
store_kvcache).AiterAttnBackend.forward_decodethat useslaunch_reshape_and_cache_flash(an existing Triton kernel already usedfor SWA models) to fuse the cast and store into a single kernel launch.
Modifications
Accuracy Tests
Speed Tests and Profiling
+2.5% output throughput at conc=64, +2.3% at conc=32, up to +5.9% at
conc=4. No regression at conc=128 (+0.4%).
Checklist
Review and Merge Process
/tag-and-rerun-ci,/tag-run-ci-label,/rerun-failed-ci