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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.6k 252

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 827 182

  3. riscv-arch-test riscv-arch-test Public

    Assembly 636 254

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 450 98

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 357 105

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 200 57

Repositories

Showing 10 of 35 repositories
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 146 CC-BY-4.0 28 4 2 Updated Jan 16, 2026
  • riscv-arch-test Public
    riscv-non-isa/riscv-arch-test’s past year of commit activity
    Assembly 636 Apache-2.0 254 60 59 Updated Jan 14, 2026
  • rvv-intrinsic-doc Public
    riscv-non-isa/rvv-intrinsic-doc’s past year of commit activity
    C 357 BSD-3-Clause 105 26 9 Updated Jan 13, 2026
  • server-soc Public

    The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.

    riscv-non-isa/server-soc’s past year of commit activity
    TeX 29 CC-BY-4.0 13 1 2 Updated Jan 13, 2026
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 200 CC-BY-4.0 57 18 5 Updated Jan 9, 2026
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    C 37 CC-BY-4.0 9 3 2 Updated Jan 9, 2026
  • riscv-server-platform Public

    The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.

    riscv-non-isa/riscv-server-platform’s past year of commit activity
    TeX 22 CC-BY-4.0 13 4 1 Updated Jan 8, 2026
  • riscv-toolchain-conventions Public

    Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

    riscv-non-isa/riscv-toolchain-conventions’s past year of commit activity
    Makefile 151 CC-BY-4.0 46 11 3 Updated Jan 7, 2026
  • hart-trace-interface Public

    This Fast-Track will extract the Hart-Trace Interface chapter from the E-Trace spec and turn it into a standalone spec

    riscv-non-isa/hart-trace-interface’s past year of commit activity
    Makefile 1 CC-BY-4.0 1 3 0 Updated Jan 6, 2026
  • riscv-ras-eri Public

    The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors, and configuration.

    riscv-non-isa/riscv-ras-eri’s past year of commit activity
    TeX 10 CC-BY-4.0 7 0 1 Updated Jan 4, 2026
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