[ci] Add riscv opt-int build by zhangfeiv0 · Pull Request #143979 · pytorch/pytorch

zhangfeiv0 · 2024-12-30T08:23:50Z

Hi, @malfet
Based on the previous discussion:

RISCV CI support · Issue #141550 · pytorch/pytorch

I have cross-compiled PyTorch for the RISC-V architecture on x86_64 Ubuntu 24.04 and created a new PR for it. Could you please help review it?

cc @malfet @seemethere

pytorch-bot · 2024-12-30T08:23:53Z

🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/143979

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✅ You can merge normally! (1 Unrelated Failure)

As of commit 52dea10 with merge base 33a1996 ():

UNSTABLE - The following job is marked as unstable, possibly due to flakiness on trunk:

pull / linux-jammy-py3_9-clang9-xla / test (xla, 1, 1, lf.linux.12xlarge, unstable) (gh) (#158876)
sccache: error: couldn't connect to server

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zhangfeiv0 · 2025-01-09T07:04:15Z

Hi, @malfet

Here’s a gentle ping: we have fixed some code errors detected by the CI. When you have time, could you please take a look and provide any suggestions?

zhangfeiv0 · 2025-01-10T05:15:53Z

@Skylion007 Could you help review it if you have time?

wangfanv0 · 2025-01-16T15:39:17Z

@malfet @Skylion007

malfet · 2025-02-20T09:45:07Z

@zhangfeiv0 Do you mind changing it to opt-in only for now and delete binary wheels workflow? Let's see if builds are passing first and than we can take next steps.

malfet · 2025-02-20T10:57:01Z

@pytorchbot rebase

pytorch-bot · 2025-02-20T10:57:21Z

Unknown label ciflow/riscv64.
Currently recognized labels are

ciflow/binaries
ciflow/binaries_libtorch
ciflow/binaries_wheel
ciflow/inductor
ciflow/inductor-periodic
ciflow/inductor-rocm
ciflow/inductor-perf-compare
ciflow/inductor-micro-benchmark
ciflow/inductor-micro-benchmark-cpu-x86
ciflow/inductor-cu126
ciflow/linux-aarch64
ciflow/mps
ciflow/nightly
ciflow/periodic
ciflow/rocm
ciflow/s390
ciflow/slow
ciflow/trunk
ciflow/unstable
ciflow/xpu
ciflow/torchbench
ciflow/autoformat

malfet · 2025-02-20T10:57:38Z

@pytorchbot rebase

pytorchmergebot · 2025-02-20T10:58:29Z

@pytorchbot started a rebase job onto refs/remotes/origin/viable/strict. Check the current status here

pytorchmergebot · 2025-02-20T10:58:33Z

Successfully rebased riscv_ci_support onto refs/remotes/origin/viable/strict, please pull locally before adding more changes (for example, via git checkout riscv_ci_support && git pull --rebase)

pytorchmergebot · 2025-02-20T10:59:07Z

@pytorchbot started a rebase job onto refs/remotes/origin/viable/strict. Check the current status here

pytorchmergebot · 2025-02-20T10:59:09Z

Tried to rebase and push PR #143979, but it was already up to date. Try rebasing against main by issuing:
@pytorchbot rebase -b main

.github/workflows/riscv64.yml

malfet · 2025-02-20T11:23:50Z

Making some changes to the workflow now. If it finished build in reasonable amount of time, than yes, it could be landed as an opt-in for now

malfet · 2025-02-21T06:52:37Z

@zhangfeiv0, you'll need to adapt your PR to make it work with CI build, i.e. docker for CI is build using files in .ci/docker folder, rather than in .ci/docker/manywheel, and are stored on ECR/ghcr.io rather than on docker hub

.ci/docker/ubuntu-riscv/Dockerfile

.ci/docker/build.sh

.ci/docker/ubuntu-riscv/Dockerfile

.github/workflows/riscv64.yml

.ci/docker/ubuntu-riscv/Dockerfile

.github/workflows/_linux-build.yml

Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>

malfet

LGTM, thank you for all the updates

malfet · 2025-08-13T16:10:16Z

@pytorchbot merge -f "This is opt-in CI PR, and lint is green"

pytorchmergebot · 2025-08-13T16:11:52Z

Merge started

Your change will be merged immediately since you used the force (-f) flag, bypassing any CI checks (ETA: 1-5 minutes). Please use -f as last resort and instead consider -i/--ignore-current to continue the merge ignoring current failures. This will allow currently pending tests to finish and report signal before the merge.

Learn more about merging in the wiki.

Questions? Feedback? Please reach out to the PyTorch DevX Team

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@malfet

Hi, @malfet Based on the previous discussion: [RISCV CI support · Issue #141550 · pytorch/pytorch](#141550) I have cross-compiled PyTorch for the RISC-V architecture on x86_64 Ubuntu 24.04 and created a new PR for it. Could you please help review it? Pull Request resolved: #143979 Approved by: https://github.com/malfet Co-authored-by: Nikita Shulga <2453524+malfet@users.noreply.github.com>

@malfet

Hi, @malfet Based on the previous discussion: [RISCV CI support · Issue #141550 · pytorch/pytorch](#141550) I have cross-compiled PyTorch for the RISC-V architecture on x86_64 Ubuntu 24.04 and created a new PR for it. Could you please help review it? Pull Request resolved: #143979 Approved by: https://github.com/malfet Co-authored-by: Nikita Shulga <2453524+malfet@users.noreply.github.com>

@malfet

Hi, @malfet Based on the previous discussion: [RISCV CI support · Issue pytorch#141550 · pytorch/pytorch](pytorch#141550) I have cross-compiled PyTorch for the RISC-V architecture on x86_64 Ubuntu 24.04 and created a new PR for it. Could you please help review it? Pull Request resolved: pytorch#143979 Approved by: https://github.com/malfet Co-authored-by: Nikita Shulga <2453524+malfet@users.noreply.github.com>

@malfet

Hi, @malfet Based on the previous discussion: [RISCV CI support · Issue pytorch#141550 · pytorch/pytorch](pytorch#141550) I have cross-compiled PyTorch for the RISC-V architecture on x86_64 Ubuntu 24.04 and created a new PR for it. Could you please help review it? Pull Request resolved: pytorch#143979 Approved by: https://github.com/malfet Co-authored-by: Nikita Shulga <2453524+malfet@users.noreply.github.com>

zhangfeiv0 requested review from a team and jeffdaily as code owners December 30, 2024 08:23

pytorch-bot bot added the release notes: releng release notes category label Dec 30, 2024

pytorchbot added the open source label Dec 30, 2024

colesbury requested a review from malfet December 30, 2024 14:48

colesbury added module: build Build system issues triaged This issue has been looked at a team member, and triaged and prioritized into an appropriate module module: risc-v All issues related to RISC-V architecture labels Dec 30, 2024

zhangfeiv0 force-pushed the riscv_ci_support branch from b02c8e9 to db6cd9f Compare January 10, 2025 03:13

zhangfeiv0 mentioned this pull request Feb 20, 2025

[RFC] Request for Feedback and Review on PRs Adding RISC-V and RVV Support #147513

Open

malfet added the ciflow/riscv64 label Feb 20, 2025

pytorchmergebot force-pushed the riscv_ci_support branch from db6cd9f to a95b721 Compare February 20, 2025 10:58

malfet reviewed Feb 20, 2025

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malfet changed the title ~~[ci] Add riscv support~~ [ci] Add riscv opt-int build Feb 20, 2025

zhangfeiv0 force-pushed the riscv_ci_support branch from ec23188 to 4c8a8c9 Compare July 26, 2025 02:04

malfet reviewed Jul 28, 2025

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zhangfeiv0 and others added 12 commits August 4, 2025 13:55

ci: add riscv support

b7467a3

Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>

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zhangfeiv0 force-pushed the riscv_ci_support branch from 52f21d0 to 0ebe723 Compare August 4, 2025 05:57

ci: Update

52dea10

Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>

zhangfeiv0 force-pushed the riscv_ci_support branch from 0ebe723 to 52dea10 Compare August 4, 2025 08:11

zhangfeiv0 requested a review from malfet August 5, 2025 06:49

malfet approved these changes Aug 13, 2025

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pytorchmergebot added the merging label Aug 13, 2025

pytorchmergebot closed this in db32b60 Aug 13, 2025

pytorchmergebot added Merged and removed merging labels Aug 13, 2025

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