Use relaxed memory ordering for Triton atomics on AMDGPU.#3945
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/3945
Note: Links to docs will display an error until the docs builds have been completed. ✅ You can merge normally! (1 Unrelated Failure)As of commit 14d3791 with merge base be10b2d ( BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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Interesting, I'm surprised the performance impact is so outsized on AMD but not CUDA. I just tested these changes locally on b200 and the results were virtually identical. Thanks for improving this! Please use |
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| "SPLIT_K": lambda args: 1 | ||
| if args["IS_BFLOAT16"] | ||
| else args["SPLIT_K"], # atomic add not supported for bfloat16 | ||
| "BLOCK_K": lambda args: ( |
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odd this formatting was changed, is your ruff version freshly pip installed from requirements.txt
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I directly installed ruff with pip without installing it from dev-requirements.txt. It seems that the ruff version that I used was 0.15.2, which was newer than 0.11.6. Now I reintalled ruff 0.11.6 and rerun formatting on this file but it didn't make it to the original format. Let me know what you would like to do it. Shall I revert to the original format or can we keep this format change as is?
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I see yeah just revert the formattting changes to this file please
…kernels The existing autotune configs for the MoE training FP8 kernels use a single configuration each (e.g., num_warps=4, num_stages=4, one block size), which prevents Triton's autotuner from finding better configs for different hardware targets. Expand the search space to cover: - Multiple num_warps values (4, 8) to better saturate both NVIDIA (warp size 32) and AMD (wavefront size 64) GPU compute units - Multiple num_stages values for software pipelining flexibility across different cache hierarchies - Multiple block sizes to adapt to varying matrix dimensions This is complementary to PR pytorch#3945 (relaxed atomics on AMDGPU) and targets the same kernels.
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@wenchenvincent looks like there is still an issue: |
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Sorry, my bad! Had an omission when reverting and adding the changes. It should be fixed now. |
… performance (#3952) * Expand Triton autotune configs for MoE FP8 rowwise and jagged scales kernels The existing autotune configs for the MoE training FP8 kernels use a single configuration each (e.g., num_warps=4, num_stages=4, one block size), which prevents Triton's autotuner from finding better configs for different hardware targets. Expand the search space to cover: - Multiple num_warps values (4, 8) to better saturate both NVIDIA (warp size 32) and AMD (wavefront size 64) GPU compute units - Multiple num_stages values for software pipelining flexibility across different cache hierarchies - Multiple block sizes to adapt to varying matrix dimensions This is complementary to PR #3945 (relaxed atomics on AMDGPU) and targets the same kernels. * Gate expanded autotune configs to AMD only, preserve original NVIDIA configs H100 benchmarks showed ~18% regression on the atomic kernel with the expanded search space. The autotuner appears to pick suboptimal configs from the larger candidate set on NVIDIA. Gate the expanded configs behind torch.version.hip so AMD gets the broader search (4-7% faster on MI250X) while NVIDIA keeps the original tuned configs. * Widen autotune search space and add N_GROUPS to scales kernel autotuning key Two improvements based on MI300X (gfx942) benchmarking: 1. float8_rowwise.py: Widen block size search space for AMD GPUs. - Atomic configs: add BLOCK_SIZE_N=256 and BLOCK_SIZE_K=64 - Reduction configs: add BLOCK_SIZE_N=128, BLOCK_SIZE_K=64, and num_stages=2,4 - Yields 1.5-2.2x speedup on MI300X for the atomic kernel and 1.05-1.25x for the reduction kernel across Llama4 MoE shapes. 2. jagged_float8_scales.py: Add N_GROUPS to autotuning key for both rowwise and colwise scales kernels. The previous key (M or K only) caused the autotuner to cache a single config across all n_groups values, but optimal tile sizes differ significantly by n_groups. This eliminates cross-n_groups interference and allows each n_groups value to independently find its best config.
tl.atomic_addand the like needs to use relaxed memory ordering on AMDGPU for performance. When the default acquire-release semantic is used, memory fence will be inserted before and after the atomics op and thus hurts performance. Such memory fences are not necessary for the functionality ofatomic_addand the like (they usually required fortl.atomic_xchg).Here is an example result when running the benchmarking for
python benchmarks/prototype/moe_training/fp8_rowwise/bench_triton_fp8_rowwise_3d_transpose_rhs.pyBefore the changes:


After the change: