…LETE + 5f.4 wireup gap identified (#1486)

## Summary

Same-day continuation of §51 cascade landed PR #1479 (FALSIFY-007
encoder/decoder validator) and PR #1481 (load_init_tensors_from_apr).
PR #1483 (5f.3 populate) and PR #1482 (contract status bump) are
MERGEABLE in queue. All 8 falsifiers in `apr-pretrain-arch-polymorphic-v1`
are now PARTIAL_ALGORITHM_LEVEL bound on main or about to land.

§52 records:
1. Updated falsifier scoreboard (8/8 vs §51's 7/8)
2. NEW step 5f.4 (CLI wireup, ~150 LOC) identified via live source
   inspection of `apr-cli/src/commands/pretrain.rs:259-297`
3. Step 5g LIVE 500-step fine-tune is now gated on 5f.4 landing first

## Why now

Per `feedback_falsifier_first_cascade_pattern.md`: when a saturated
auto-merge queue blocks more impl PRs (#1483 + #1482 both in queue
touching pretrain_real.rs), switch to non-conflicting work. This spec
amendment touches one markdown file with no PR conflicts.

## Five Whys (§52.8 in body)

1. Why didn't §50 catch 5f.4? — top-down arch-coupling lens missed the
   CLI-dispatch seam.
2. Why is 5f.4 separate from 5f.3? — different crate (apr-cli vs
   aprender-train).
3. Why must 5f.4 be atomic? — removing "not yet wired" Err without the
   wireup produces silent random-init (§28 SHIP-007 defect class).
4. Why ~150 LOC? — 4 levels of plumbing + new builder + tests + CUDA.
5. Why call 5f.4 out in spec? — without §52, readers would assume 5g
   is dispatchable; spec is the source of truth.

## Test plan

- [x] Single markdown file, no Rust changes
- [x] Falsifier scoreboard table updated to 8/8 PARTIAL_ALGORITHM_LEVEL
- [x] Step roadmap table adds 5f.4 between 5f.3 and 5g
- [x] Cadence preserved: §41 → ... → §51 → §52 (12 amendments since 2026-05-03)

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>

…ION-COMPLETE; contract v1.1.0 → v1.2.0 FUNCTIONAL (#1495)

§50.4 cascade INTEGRATION-COMPLETE on main with PR #1494 merging at
2026-05-05T01:48:14Z. The `apr pretrain --init <PATH>` flow is now
end-to-end functional on CPU; the legacy "not yet wired" Err is
RETIRED; step 5g LIVE is the only remaining gate before MODEL-2 ship-%
can move from 57% → ≥58%.

Spec amendment §53:
- Updated falsifier scoreboard: 6/8 INTEGRATION (001/002/003/005/006/007
  via live CLI dispatch); 2/8 PARTIAL_ALGORITHM_LEVEL (004 forward-pass
  smoke + 008 contract validation are inherently algorithm-level).
- Step roadmap: 5a-5f.4 ✅ MERGED; 5f.5 (CUDA wireup) NOT YET STARTED;
  5g (LIVE 500-step fine-tune) operator-dispatchable on RTX 4090.
- Cascade ships statistics: 11 PRs over 2 days
  (#1471/#1472/#1473/#1474/#1475/#1476/#1478/#1479/#1481/#1482/#1483/#1486/#1494).
- MODEL-1 ship % unchanged at 91%; MODEL-2 ship % unchanged at 57%
  (gated on 5g empirical val_loss < 9.38 evidence).
- 3 CI andon classes documented as feedback memories during cascade
  (workspace-test missing-binary, trueno SIGSEGV-on-cleanup, auto-merge
  behind-state).

Contract apr-pretrain-arch-polymorphic-v1 v1.1.0 → v1.2.0 FUNCTIONAL:
- All 8 falsifiers PASS on main; 6/8 reach INTEGRATION via the
  user-facing `apr pretrain --init` flow.
- verification_summary updated: tested 7 → 8; status partial →
  functional.
- Added §52 + §53 references.
- Promotion to DISCHARGED still requires §50.4 step 5g LIVE empirical
  500-step fine-tune on canonical Qwen2.5-Coder-0.5B-Instruct.apr
  producing val_loss < 9.38.

`pv validate contracts/apr-pretrain-arch-polymorphic-v1.yaml` exits 0.

Refs: SPEC-SHIP-TWO-001 §50.4 cascade, PR #1494 merge commit 9afca16

Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>