Hi there, I've been doing some testing on intel based gigabyte motherboards and have identified some issues with the isa bridge mmio implementation. I've been developing the it87 driver over on linux using the bridge code here as a base, and based on testing, intel systems cannot have two mmio bridge windows active at the same time. The addresses simply conflict and you end up with the last set window being active. So the implementation will need to be fixed. This code was introduced with #26 . Let me know if you need more information. As on skylake there may need to be more steps to properly enable the mmio windows (pending testing).