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First, since the internal register is kept in CPU cycles (not RCP cycles), we need to double the value written via MTC0/DMTC0. Second, writing a count equal to compare would cause an infinite loop because the fault would be triggered while PC was on the instruction doing MTC0 itself, which would be then re-executed at the end of the exception. On real hardware, in general, when COUNT==COMPARE, the interrupt happens a few cycles later, enough for PC to move to other opcodes. Instead of trying to implement this, I've simply made sure that the interrupt happened after the opcode was executed rather than before. Also, since the internal counter is in CPU cycles, we make sure to only raise the CAUSE bit once.
rasky
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Jun 21, 2021
It used to hang cen64 (but not Ares or dgb-n64). I fixed it here: n64dev/cen64#201 so it now works with updated versions of cen64. Reenable it.
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First, since the internal register is kept in CPU cycles (not RCP cycles),
we need to double the value written via MTC0/DMTC0.
Second, writing a count equal to compare would cause an infinite loop
because the fault would be triggered while PC was on the instruction
doing MTC0 itself, which would be then re-executed at the end of the
exception. On real hardware, in general, when COUNT==COMPARE, the
interrupt happens a few cycles later, enough for PC to move to other
opcodes. Instead of trying to implement this, I've simply made sure
that the interrupt happened after the opcode was executed rather than
before. Also, since the internal counter is in CPU cycles, we make
sure to only raise the CAUSE bit once.
Attached is libdragon test ROM which stops in an infinite loop on
current master, and works after this PR.
testrom_emu.zip