[SelectionDAG] Remove the remaining NoSignedZerosFPMath use#201535
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-backend-aarch64 Author: paperchalice ChangesThis should be the last use in CodeGen part. Patch is 44.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201535.diff 12 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6cb9ae5fa7803..7b2a35b10c318 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19962,8 +19962,7 @@ static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
TLI.isOperationLegal(IntToFPOp, VT))
return SDValue();
- bool IsSignedZeroSafe = DAG.getTarget().Options.NoSignedZerosFPMath ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
+ bool IsSignedZeroSafe = DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
// For signed conversions: The optimization changes signed zero behavior.
if (IsSigned && !IsSignedZeroSafe)
return SDValue();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index eca5bb1598ae0..19472f3dd2cb9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4054,6 +4054,8 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
SDNodeFlags Flags;
if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I))
Flags.setNonNeg(PNI->hasNonNeg());
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
@@ -4063,7 +4065,11 @@ void SelectionDAGBuilder::visitSIToFP(const User &I) {
SDValue N = getValue(I.getOperand(0));
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
- setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
+ SDNodeFlags Flags;
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
+
+ setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
void SelectionDAGBuilder::visitPtrToAddr(const User &I) {
diff --git a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
index a50716e4ab183..ab219e8e30641 100644
--- a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,SIGNED-ZEROS
-; RUN: llc -mtriple=aarch64 --enable-no-signed-zeros-fp-math < %s | FileCheck %s --check-prefixes=CHECK,NO-SIGNED-ZEROS
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
; Test folding of float->int->float roundtrips into float-only operations.
; The optimization could converts patterns like:
@@ -9,62 +8,63 @@
; This is relevant for AArch64 as it avoids GPR bouncing and keeps computation in SIMD/FP registers.
define float @test_signed_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_basic:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs s0, s0
-; SIGNED-ZEROS-NEXT: scvtf s0, s0
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_basic:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_basic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs s0, s0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: ret
entry:
%i = fptosi float %x to i32
%f = sitofp i32 %i to float
ret float %f
}
+define float @test_signed_basic_nsz(float %x) {
+; CHECK-LABEL: test_signed_basic_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi float %x to i32
+ %f = sitofp nsz i32 %i to float
+ ret float %f
+}
+
define float @test_unsigned_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu s0, s0
-; SIGNED-ZEROS-NEXT: ucvtf s0, s0
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_basic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu s0, s0
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: ret
entry:
%i = fptoui float %x to i32
%f = uitofp i32 %i to float
ret float %f
}
+define float @test_unsigned_basic_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_basic_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui float %x to i32
+ %f = uitofp nsz i32 %i to float
+ ret float %f
+}
+
define float @test_signed_min_max(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs w9, s0
-; SIGNED-ZEROS-NEXT: mov w8, #-512 // =0xfffffe00
-; SIGNED-ZEROS-NEXT: cmn w9, #512
-; SIGNED-ZEROS-NEXT: csel w8, w9, w8, gt
-; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
-; SIGNED-ZEROS-NEXT: cmp w8, #1023
-; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lt
-; SIGNED-ZEROS-NEXT: scvtf s0, w8
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #196, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-512 // =0xfffffe00
+; CHECK-NEXT: cmn w9, #512
+; CHECK-NEXT: csel w8, w9, w8, gt
+; CHECK-NEXT: mov w9, #1023 // =0x3ff
+; CHECK-NEXT: cmp w8, #1023
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: ret
entry:
%i = fptosi float %x to i32
%lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
@@ -73,29 +73,37 @@ entry:
ret float %f
}
+define float @test_signed_min_max_nsz(float %x) {
+; CHECK-LABEL: test_signed_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2s, #196, lsl #24
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi float %x to i32
+ %lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
+ %clamped = call i32 @llvm.smin.i32(i32 %lower, i32 1023)
+ %f = sitofp nsz i32 %clamped to float
+ ret float %f
+}
+
define float @test_unsigned_min_max(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu w9, s0
-; SIGNED-ZEROS-NEXT: mov w8, #512 // =0x200
-; SIGNED-ZEROS-NEXT: cmp w9, #512
-; SIGNED-ZEROS-NEXT: csel w8, w9, w8, hi
-; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
-; SIGNED-ZEROS-NEXT: cmp w8, #1023
-; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lo
-; SIGNED-ZEROS-NEXT: ucvtf s0, w8
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #68, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu w9, s0
+; CHECK-NEXT: mov w8, #512 // =0x200
+; CHECK-NEXT: cmp w9, #512
+; CHECK-NEXT: csel w8, w9, w8, hi
+; CHECK-NEXT: mov w9, #1023 // =0x3ff
+; CHECK-NEXT: cmp w8, #1023
+; CHECK-NEXT: csel w8, w8, w9, lo
+; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: ret
entry:
%i = fptoui float %x to i32
%lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
@@ -104,6 +112,25 @@ entry:
ret float %f
}
+define float @test_unsigned_min_max_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2s, #68, lsl #24
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui float %x to i32
+ %lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
+ %clamped = call i32 @llvm.umin.i32(i32 %lower, i32 1023)
+ %f = uitofp nsz i32 %clamped to float
+ ret float %f
+}
+
; 16777217 is NOT exactly representable in f32.
define float @test_inexact_16777217(float %x) {
; CHECK-LABEL: test_inexact_16777217:
@@ -124,94 +151,107 @@ entry:
}
define <4 x float> @test_signed_v4f32(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v4f32:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptosi <4 x float> %x to <4 x i32>
%f = sitofp <4 x i32> %i to <4 x float>
ret <4 x float> %f
}
+define <4 x float> @test_signed_v4f32_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_signed_v4f32_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <4 x float> %x to <4 x i32>
+ %f = sitofp nsz <4 x i32> %i to <4 x float>
+ ret <4 x float> %f
+}
+
define <4 x float> @test_unsigned_v4f32(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptoui <4 x float> %x to <4 x i32>
%f = uitofp <4 x i32> %i to <4 x float>
ret <4 x float> %f
}
+define <4 x float> @test_unsigned_v4f32_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_unsigned_v4f32_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <4 x float> %x to <4 x i32>
+ %f = uitofp nsz <4 x i32> %i to <4 x float>
+ ret <4 x float> %f
+}
+
define <2 x double> @test_signed_v2f64(<2 x double> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v2f64:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: scvtf v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v2f64:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: ret
entry:
%i = fptosi <2 x double> %x to <2 x i64>
%f = sitofp <2 x i64> %i to <2 x double>
ret <2 x double> %f
}
+define <2 x double> @test_signed_v2f64_nsz(<2 x double> %x) {
+; CHECK-LABEL: test_signed_v2f64_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <2 x double> %x to <2 x i64>
+ %f = sitofp nsz <2 x i64> %i to <2 x double>
+ ret <2 x double> %f
+}
+
define <2 x double> @test_unsigned_v2f64(<2 x double> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ucvtf v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: ret
entry:
%i = fptoui <2 x double> %x to <2 x i64>
%f = uitofp <2 x i64> %i to <2 x double>
ret <2 x double> %f
}
+define <2 x double> @test_unsigned_v2f64_nsz(<2 x double> %x) {
+; CHECK-LABEL: test_unsigned_v2f64_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <2 x double> %x to <2 x i64>
+ %f = uitofp nsz <2 x i64> %i to <2 x double>
+ ret <2 x double> %f
+}
+
define <4 x float> @test_signed_v4f32_min_max(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: mvni v1.4s, #1, msl #8
-; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
-; SIGNED-ZEROS-NEXT: smax v0.4s, v0.4s, v1.4s
-; SIGNED-ZEROS-NEXT: smin v0.4s, v0.4s, v2.4s
-; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #196, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mvni v1.4s, #1, msl #8
+; CHECK-NEXT: movi v2.4s, #3, msl #8
+; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptosi <4 x float> %x to <4 x i32>
%lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
@@ -220,27 +260,35 @@ entry:
ret <4 x float> %f
}
+define <4 x float> @test_signed_v4f32_min_max_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_signed_v4f32_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #196, lsl #24
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <4 x float> %x to <4 x i32>
+ %lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
+ %clamped = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
+ %f = sitofp nsz <4 x i32> %clamped to <4 x float>
+ ret <4 x float> %f
+}
+
define <4 x float> @test_unsigned_v4f32_min_max(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: movi v1.4s, #2, lsl #8
-; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
-; SIGNED-ZEROS-NEXT: umax v0.4s, v0.4s, v1.4s
-; SIGNED-ZEROS-NEXT: umin v0.4s, v0.4s, v2.4s
-; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #68, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #2, lsl #8
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: movi v2.4s, #3, msl #8
+; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptoui <4 x float> %x to <4 x i32>
%lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
@@ -249,6 +297,25 @@ entry:
ret <4 x float> %f
}
+define <4 x float> @test_unsigned_v4f32_min_max_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_unsigned_v4f32_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #68, lsl #24
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <4 x float> %x to <4 x i32>
+ %lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
+ %clamped = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
+ %f = uitofp nsz <4 x i32> %clamped to <4 x float>
+ ret <4 x float> %f
+}
+
define i1 @test_fcmp(float %x) {
; CHECK-LABEL: test_fcmp:
diff --git a/llvm/test/CodeGen/AArch64/ftrunc.ll b/llvm/test/CodeGen/AArch64/ftrunc.ll
index c7bf514e902be..093262160af97 100644
--- a/llvm/test/CodeGen/AArch64/ftrunc.ll
+++ b/llvm/test/CodeGen/AArch64/ftrunc.ll
@@ -1,45 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
-define float @trunc_unsigned_f32(float %x) #0 {
+define float @trunc_unsigned_f32(float %x) {
; CHECK-LABEL: trunc_unsigned_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptoui float %x to i32
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_unsigned_f64(double %x) #0 {
+define double @trunc_unsigned_f64(double %x) {
; CHECK-LABEL: trunc_unsigned_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptoui double %x to i64
- %r = uitofp i64 %i to double
+ %r = uitofp nsz i64 %i to double
ret double %r
}
-define float @trunc_signed_f32(float %x) #0 {
+define float @trunc_signed_f32(float %x) {
; CHECK-LABEL: trunc_signed_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_signed_f64(double %x) #0 {
+define double @trunc_signed_f64(double %x) {
; CHECK-LABEL: trunc_signed_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
index 26cab6d542c65..74ba9c5eaf4da 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
@@ -22,7 +22,7 @@ define <8 x float> @frintz_f32_i32_f32(<8 x float> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%res = fptosi <8 x float> %in to <8 x i32>
- %res2 = sitofp <8 x i32> %res to <8 x float>
+ %res2 = sitofp nsz <8 x i32> %res to <8 x float>
ret <8 x float> %res2
}
@@ -41,7 +41,7 @@ define <4 x double> @frintz_f64_i32_f64(<4 x double> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 kille...
[truncated]
|
|
@llvm/pr-subscribers-backend-x86 Author: paperchalice ChangesThis should be the last use in CodeGen part. Patch is 44.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201535.diff 12 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6cb9ae5fa7803..7b2a35b10c318 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19962,8 +19962,7 @@ static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
TLI.isOperationLegal(IntToFPOp, VT))
return SDValue();
- bool IsSignedZeroSafe = DAG.getTarget().Options.NoSignedZerosFPMath ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
+ bool IsSignedZeroSafe = DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
// For signed conversions: The optimization changes signed zero behavior.
if (IsSigned && !IsSignedZeroSafe)
return SDValue();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index eca5bb1598ae0..19472f3dd2cb9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4054,6 +4054,8 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
SDNodeFlags Flags;
if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I))
Flags.setNonNeg(PNI->hasNonNeg());
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
@@ -4063,7 +4065,11 @@ void SelectionDAGBuilder::visitSIToFP(const User &I) {
SDValue N = getValue(I.getOperand(0));
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
- setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
+ SDNodeFlags Flags;
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
+
+ setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
void SelectionDAGBuilder::visitPtrToAddr(const User &I) {
diff --git a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
index a50716e4ab183..ab219e8e30641 100644
--- a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,SIGNED-ZEROS
-; RUN: llc -mtriple=aarch64 --enable-no-signed-zeros-fp-math < %s | FileCheck %s --check-prefixes=CHECK,NO-SIGNED-ZEROS
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
; Test folding of float->int->float roundtrips into float-only operations.
; The optimization could converts patterns like:
@@ -9,62 +8,63 @@
; This is relevant for AArch64 as it avoids GPR bouncing and keeps computation in SIMD/FP registers.
define float @test_signed_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_basic:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs s0, s0
-; SIGNED-ZEROS-NEXT: scvtf s0, s0
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_basic:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_basic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs s0, s0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: ret
entry:
%i = fptosi float %x to i32
%f = sitofp i32 %i to float
ret float %f
}
+define float @test_signed_basic_nsz(float %x) {
+; CHECK-LABEL: test_signed_basic_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi float %x to i32
+ %f = sitofp nsz i32 %i to float
+ ret float %f
+}
+
define float @test_unsigned_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu s0, s0
-; SIGNED-ZEROS-NEXT: ucvtf s0, s0
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_basic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu s0, s0
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: ret
entry:
%i = fptoui float %x to i32
%f = uitofp i32 %i to float
ret float %f
}
+define float @test_unsigned_basic_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_basic_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui float %x to i32
+ %f = uitofp nsz i32 %i to float
+ ret float %f
+}
+
define float @test_signed_min_max(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs w9, s0
-; SIGNED-ZEROS-NEXT: mov w8, #-512 // =0xfffffe00
-; SIGNED-ZEROS-NEXT: cmn w9, #512
-; SIGNED-ZEROS-NEXT: csel w8, w9, w8, gt
-; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
-; SIGNED-ZEROS-NEXT: cmp w8, #1023
-; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lt
-; SIGNED-ZEROS-NEXT: scvtf s0, w8
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #196, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-512 // =0xfffffe00
+; CHECK-NEXT: cmn w9, #512
+; CHECK-NEXT: csel w8, w9, w8, gt
+; CHECK-NEXT: mov w9, #1023 // =0x3ff
+; CHECK-NEXT: cmp w8, #1023
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: ret
entry:
%i = fptosi float %x to i32
%lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
@@ -73,29 +73,37 @@ entry:
ret float %f
}
+define float @test_signed_min_max_nsz(float %x) {
+; CHECK-LABEL: test_signed_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2s, #196, lsl #24
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi float %x to i32
+ %lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
+ %clamped = call i32 @llvm.smin.i32(i32 %lower, i32 1023)
+ %f = sitofp nsz i32 %clamped to float
+ ret float %f
+}
+
define float @test_unsigned_min_max(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu w9, s0
-; SIGNED-ZEROS-NEXT: mov w8, #512 // =0x200
-; SIGNED-ZEROS-NEXT: cmp w9, #512
-; SIGNED-ZEROS-NEXT: csel w8, w9, w8, hi
-; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
-; SIGNED-ZEROS-NEXT: cmp w8, #1023
-; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lo
-; SIGNED-ZEROS-NEXT: ucvtf s0, w8
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #68, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu w9, s0
+; CHECK-NEXT: mov w8, #512 // =0x200
+; CHECK-NEXT: cmp w9, #512
+; CHECK-NEXT: csel w8, w9, w8, hi
+; CHECK-NEXT: mov w9, #1023 // =0x3ff
+; CHECK-NEXT: cmp w8, #1023
+; CHECK-NEXT: csel w8, w8, w9, lo
+; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: ret
entry:
%i = fptoui float %x to i32
%lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
@@ -104,6 +112,25 @@ entry:
ret float %f
}
+define float @test_unsigned_min_max_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2s, #68, lsl #24
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui float %x to i32
+ %lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
+ %clamped = call i32 @llvm.umin.i32(i32 %lower, i32 1023)
+ %f = uitofp nsz i32 %clamped to float
+ ret float %f
+}
+
; 16777217 is NOT exactly representable in f32.
define float @test_inexact_16777217(float %x) {
; CHECK-LABEL: test_inexact_16777217:
@@ -124,94 +151,107 @@ entry:
}
define <4 x float> @test_signed_v4f32(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v4f32:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptosi <4 x float> %x to <4 x i32>
%f = sitofp <4 x i32> %i to <4 x float>
ret <4 x float> %f
}
+define <4 x float> @test_signed_v4f32_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_signed_v4f32_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <4 x float> %x to <4 x i32>
+ %f = sitofp nsz <4 x i32> %i to <4 x float>
+ ret <4 x float> %f
+}
+
define <4 x float> @test_unsigned_v4f32(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptoui <4 x float> %x to <4 x i32>
%f = uitofp <4 x i32> %i to <4 x float>
ret <4 x float> %f
}
+define <4 x float> @test_unsigned_v4f32_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_unsigned_v4f32_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <4 x float> %x to <4 x i32>
+ %f = uitofp nsz <4 x i32> %i to <4 x float>
+ ret <4 x float> %f
+}
+
define <2 x double> @test_signed_v2f64(<2 x double> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v2f64:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: scvtf v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v2f64:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: ret
entry:
%i = fptosi <2 x double> %x to <2 x i64>
%f = sitofp <2 x i64> %i to <2 x double>
ret <2 x double> %f
}
+define <2 x double> @test_signed_v2f64_nsz(<2 x double> %x) {
+; CHECK-LABEL: test_signed_v2f64_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <2 x double> %x to <2 x i64>
+ %f = sitofp nsz <2 x i64> %i to <2 x double>
+ ret <2 x double> %f
+}
+
define <2 x double> @test_unsigned_v2f64(<2 x double> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ucvtf v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: ret
entry:
%i = fptoui <2 x double> %x to <2 x i64>
%f = uitofp <2 x i64> %i to <2 x double>
ret <2 x double> %f
}
+define <2 x double> @test_unsigned_v2f64_nsz(<2 x double> %x) {
+; CHECK-LABEL: test_unsigned_v2f64_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <2 x double> %x to <2 x i64>
+ %f = uitofp nsz <2 x i64> %i to <2 x double>
+ ret <2 x double> %f
+}
+
define <4 x float> @test_signed_v4f32_min_max(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: mvni v1.4s, #1, msl #8
-; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
-; SIGNED-ZEROS-NEXT: smax v0.4s, v0.4s, v1.4s
-; SIGNED-ZEROS-NEXT: smin v0.4s, v0.4s, v2.4s
-; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #196, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mvni v1.4s, #1, msl #8
+; CHECK-NEXT: movi v2.4s, #3, msl #8
+; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptosi <4 x float> %x to <4 x i32>
%lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
@@ -220,27 +260,35 @@ entry:
ret <4 x float> %f
}
+define <4 x float> @test_signed_v4f32_min_max_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_signed_v4f32_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #196, lsl #24
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <4 x float> %x to <4 x i32>
+ %lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
+ %clamped = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
+ %f = sitofp nsz <4 x i32> %clamped to <4 x float>
+ ret <4 x float> %f
+}
+
define <4 x float> @test_unsigned_v4f32_min_max(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: movi v1.4s, #2, lsl #8
-; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
-; SIGNED-ZEROS-NEXT: umax v0.4s, v0.4s, v1.4s
-; SIGNED-ZEROS-NEXT: umin v0.4s, v0.4s, v2.4s
-; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #68, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #2, lsl #8
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: movi v2.4s, #3, msl #8
+; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptoui <4 x float> %x to <4 x i32>
%lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
@@ -249,6 +297,25 @@ entry:
ret <4 x float> %f
}
+define <4 x float> @test_unsigned_v4f32_min_max_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_unsigned_v4f32_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #68, lsl #24
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <4 x float> %x to <4 x i32>
+ %lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
+ %clamped = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
+ %f = uitofp nsz <4 x i32> %clamped to <4 x float>
+ ret <4 x float> %f
+}
+
define i1 @test_fcmp(float %x) {
; CHECK-LABEL: test_fcmp:
diff --git a/llvm/test/CodeGen/AArch64/ftrunc.ll b/llvm/test/CodeGen/AArch64/ftrunc.ll
index c7bf514e902be..093262160af97 100644
--- a/llvm/test/CodeGen/AArch64/ftrunc.ll
+++ b/llvm/test/CodeGen/AArch64/ftrunc.ll
@@ -1,45 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
-define float @trunc_unsigned_f32(float %x) #0 {
+define float @trunc_unsigned_f32(float %x) {
; CHECK-LABEL: trunc_unsigned_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptoui float %x to i32
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_unsigned_f64(double %x) #0 {
+define double @trunc_unsigned_f64(double %x) {
; CHECK-LABEL: trunc_unsigned_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptoui double %x to i64
- %r = uitofp i64 %i to double
+ %r = uitofp nsz i64 %i to double
ret double %r
}
-define float @trunc_signed_f32(float %x) #0 {
+define float @trunc_signed_f32(float %x) {
; CHECK-LABEL: trunc_signed_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_signed_f64(double %x) #0 {
+define double @trunc_signed_f64(double %x) {
; CHECK-LABEL: trunc_signed_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
index 26cab6d542c65..74ba9c5eaf4da 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
@@ -22,7 +22,7 @@ define <8 x float> @frintz_f32_i32_f32(<8 x float> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%res = fptosi <8 x float> %in to <8 x i32>
- %res2 = sitofp <8 x i32> %res to <8 x float>
+ %res2 = sitofp nsz <8 x i32> %res to <8 x float>
ret <8 x float> %res2
}
@@ -41,7 +41,7 @@ define <4 x double> @frintz_f64_i32_f64(<4 x double> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 kille...
[truncated]
|
arsenm
reviewed
Jun 5, 2026
| I.getType()); | ||
| setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); | ||
| SDNodeFlags Flags; | ||
| if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) |
Contributor
There was a problem hiding this comment.
If this is SIToFP, this cannot fail?
| SDNodeFlags Flags; | ||
| if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I)) | ||
| Flags.setNonNeg(PNI->hasNonNeg()); | ||
| if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) |
| @@ -4054,6 +4054,8 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) { | |||
| SDNodeFlags Flags; | |||
| if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I)) | |||
arsenm
approved these changes
Jun 5, 2026
Comment on lines
+4055
to
+4056
| Flags.setNonNeg(cast<PossiblyNonNegInst>(&I)->hasNonNeg()); | ||
| Flags.copyFMF(*cast<FPMathOperator>(&I)); |
Contributor
There was a problem hiding this comment.
I didn't realize this ended up with 2 sets of flags
🐧 Linux x64 Test Results
Failed Tests(click on a test name to see its output) lldb-apilldb-api.iohandler/sigint/TestProcessIOHandlerInterrupt.pylldb-api.tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.pylldb-api.tools/lldb-dap/breakpoint/TestDAP_logpoints.pylldb-api.tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.pylldb-api.tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.pylldb-api.tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.pyIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
davemgreen
reviewed
Jun 5, 2026
| ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 | ||
| ; CHECK-NEXT: ret | ||
| %res = fptosi <8 x float> %in to <8 x i32> | ||
| %res2 = sitofp <8 x i32> %res to <8 x float> |
Contributor
There was a problem hiding this comment.
Can you remove the -enable-no-signed-zeros-fp-math flag now.
NoSignedZerosFPMath useNoSignedZerosFPMath use
carlobertolli
pushed a commit
to carlobertolli/llvm-project
that referenced
this pull request
Jun 11, 2026
…01535) This should be the last use in CodeGen part.
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This should be the last use in CodeGen part.