[GlobalISel][KnownBits] Port SREM to GlobalISel#198956
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This PR also move case statement for or G_SREM that is being introduced by llvm#193455 So that [u|s][div|rem] being grouped together, just like in SelectionDAG.cpp. Signed-off-by: ZakyHermawan <zaky.hermawan9615@gmail.com>
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@llvm/pr-subscribers-backend-mips @llvm/pr-subscribers-backend-aarch64 Author: Zaky Hermawan (ZakyHermawan) ChangesThis PR also move case statement for or Related: #150515 Full diff: https://github.com/llvm/llvm-project/pull/198956.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 44298258da11c..4297f6df10015 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -309,18 +309,6 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known.Zero.setHighBits(MaxValue.countl_zero());
break;
}
- case TargetOpcode::G_UREM: {
- KnownBits LHSKnown(Known.getBitWidth());
- KnownBits RHSKnown(Known.getBitWidth());
-
- computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
- Depth + 1);
- computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
- Depth + 1);
-
- Known = KnownBits::urem(LHSKnown, RHSKnown);
- break;
- }
case TargetOpcode::G_CONSTANT: {
Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());
break;
@@ -453,6 +441,30 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
MI.getFlag(MachineInstr::MIFlag::IsExact));
break;
}
+ case TargetOpcode::G_UREM: {
+ KnownBits LHSKnown(Known.getBitWidth());
+ KnownBits RHSKnown(Known.getBitWidth());
+
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
+ Depth + 1);
+
+ Known = KnownBits::urem(LHSKnown, RHSKnown);
+ break;
+ }
+ case TargetOpcode::G_SREM: {
+ KnownBits LHSKnown(Known.getBitWidth());
+ KnownBits RHSKnown(Known.getBitWidth());
+
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
+ Depth + 1);
+
+ Known = KnownBits::srem(LHSKnown, RHSKnown);
+ break;
+ }
case TargetOpcode::G_SELECT: {
computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),
Known, DemandedElts, Depth + 1);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir
new file mode 100644
index 0000000000000..598c41dd29e5b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir
@@ -0,0 +1,107 @@
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+# CHECK-LABEL: name: @srem_pow2
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+---
+name: srem_pow2
+body: |
+ bb.1:
+ liveins: $w0
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 8
+ %2:_(s32) = G_SREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @srem_non_pow2
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001010 SignBits:28
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+---
+name: srem_non_pow2
+body: |
+ bb.1:
+ liveins: $w0
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 10
+ %2:_(s32) = G_SREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @srem
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+---
+name: srem
+body: |
+ bb.1:
+ liveins: $w0, $w1
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = COPY $w1
+ %2:_(s32) = G_SREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @srem_implicit_def
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+---
+name: srem_implicit_def
+body: |
+ bb.1:
+ liveins: $w0
+
+ %0:_(s32) = G_IMPLICIT_DEF
+ %1:_(s32) = G_CONSTANT i32 8
+ %2:_(s32) = G_SREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @srem_both_implicit_def
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+---
+name: srem_both_implicit_def
+body: |
+ bb.1:
+
+ %0:_(s32) = G_IMPLICIT_DEF
+ %1:_(s32) = G_IMPLICIT_DEF
+ %2:_(s32) = G_SREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @srem_const_const
+# CHECK-NEXT: %0:_ KnownBits:00000000000000000000000000001010 SignBits:28
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000000011 SignBits:30
+# CHECK-NEXT: %2:_ KnownBits:000000000000000000000000000000?? SignBits:30
+
+---
+name: srem_const_const
+body: |
+ bb.1:
+
+ %0:_(s32) = G_CONSTANT i32 10
+ %1:_(s32) = G_CONSTANT i32 3
+ %2:_(s32) = G_SREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
|
Signed-off-by: ZakyHermawan <zaky.hermawan9615@gmail.com>
Contributor
Author
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@arsenm @davemgreen |
arsenm
requested changes
May 21, 2026
Signed-off-by: ZakyHermawan <zaky.hermawan9615@gmail.com>
🪟 Windows x64 Test Results
✅ The build succeeded and all tests passed. |
🐧 Linux x64 Test Results
✅ The build succeeded and all tests passed. |
Signed-off-by: ZakyHermawan <zaky.hermawan9615@gmail.com>
Signed-off-by: ZakyHermawan <zaky.hermawan9615@gmail.com>
arsenm
approved these changes
May 21, 2026
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This PR also move case statement for or
G_UREMthat is being introduced by #193455 So thatG_[U|S][DIV|REM]being grouped together, just like inSelectionDAG.cppRelated: #150515