[BPF] treat compiler fence as codegen no-op by bidhan-a · Pull Request #196734 · llvm/llvm-project

bidhan-a · 2026-05-09T15:48:41Z

The BPF backend has no instruction-selection pattern for ISD::ATOMIC_FENCE, so LLVM IR containing a fence instruction crashes with Cannot select: AtomicFence....

Rust code snippet

#[unsafe(no_mangle)]
pub fn entrypoint(_input: *mut u8) -> u64 {
    core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst);
    0
}

LLVM IR

; ModuleID = 'linked_module'
source_filename = "linked_module"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "bpfel"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
define dso_local noundef i64 @entrypoint(ptr noundef readnone captures(none) %0) unnamed_addr #0 {
  fence syncscope("singlethread") seq_cst
  ret i64 0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn "target-cpu"="generic" }

!llvm.ident = !{!0}

!0 = !{!"rustc version 1.97.0-nightly (f53b654a8 2026-04-30)"}

Error

LLVM ERROR: Cannot select: 0x7fcf7701a1c0: ch = AtomicFence 0x7fcf75718df8, TargetConstant:i64<7>, TargetConstant:i64<0>
In function: entrypoint

Stack dump:
          0.    Running pass 'Function Pass Manager' on module 'linked_module'.
          1.    Running pass 'BPF DAG->DAG Pattern Instruction Selection' on function '@entrypoint'

Fix

This patch lowers single-thread (compiler) fences to ISD::MEMBARRIER (no-op) and produces an error for cross-thread (runtime) fences.

github-actions · 2026-05-09T15:49:03Z

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bidhan-a · 2026-05-11T12:52:07Z

cc @yonghong-song This PR fixes a crash, please take a look.

yonghong-song · 2026-05-11T14:49:24Z

Beyond the above rust example. The below are two C examples:

  void memory_barrier(void) {
      __sync_synchronize();                                                                                        
  }

or

#include <stdatomic.h>
void memory_barrier(void) {
  __c11_atomic_thread_fence(__ATOMIC_ACQUIRE);
}

where __sync_synchronize() will generate IR 'fence seq_cst',
and __c11_atomic_thread_fence(__ATOMIC_ACQUIRE) will generate IR 'fence acquire'.

yonghong-song

LGTM.

4ast

hold on. SeqCst needs a real barrier. On x86 it's a locked stack operation.
BPF backend should do the same.
and ISD::MEMBARRIER for everything but SeqCst.
XCore is a bad analogy here, since it's single core afaik.

clairechingching · 2026-05-12T13:51:02Z

@4ast

Are you suggesting generating an atomic exchange (xchg) on a stack slot for SeqCst, similar to x86?

We can do that but my understanding is that the BPF stack is per invocation and private to the current program execution, so I’m not sure what it would synchronize against.

4ast · 2026-05-12T16:39:01Z

@4ast

Are you suggesting generating an atomic exchange (xchg) on a stack slot for SeqCst, similar to x86?

We can do that but my understanding is that the BPF stack is per invocation and private to the current program execution, so I’m not sure what it would synchronize against.

from libarena/include/bpf_atomic.h
#define smp_mb()
({
volatile unsigned long __val;
__sync_fetch_and_add(&__val, 0);
})

iirc x86 does 'lock or (rsp)' which is same idea.
__sync_fetch_and_add in BPF will eventually be JITed as 'lock xadd' on x86.

bidhan-a · 2026-05-13T11:50:19Z

@4ast
Are you suggesting generating an atomic exchange (xchg) on a stack slot for SeqCst, similar to x86?
We can do that but my understanding is that the BPF stack is per invocation and private to the current program execution, so I’m not sure what it would synchronize against.

from libarena/include/bpf_atomic.h #define smp_mb() ({ volatile unsigned long __val; __sync_fetch_and_add(&__val, 0); })

iirc x86 does 'lock or (rsp)' which is same idea. __sync_fetch_and_add in BPF will eventually be JITed as 'lock xadd' on x86.

@4ast Updated the handling for fence seq_cst as per your suggestion. Could you please take a look?

4ast

lgtm

eddyz87 · 2026-05-13T18:03:47Z

I agree with the approach, but it looks like our kernel side documentation is lacking in this regard. E.g. nothing about seq_cst in the instruction set doc. Should it be extended?

clairechingching · 2026-05-19T16:35:34Z

@yonghong-song all feedback is addressed and all checks have passed, can we merge this? I'm also wanting to back port this to fix the crash

github-actions · 2026-05-19T19:00:51Z

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@entrypoint

The BPF backend has no instruction-selection pattern for `ISD::ATOMIC_FENCE`, so LLVM IR containing a fence instruction crashes with `Cannot select: AtomicFence...`. **Rust code snippet** ``` #[unsafe(no_mangle)] pub fn entrypoint(_input: *mut u8) -> u64 { core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst); 0 } ``` **LLVM IR** ``` ; ModuleID = 'linked_module' source_filename = "linked_module" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" target triple = "bpfel" ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn define dso_local noundef i64 @entrypoint(ptr noundef readnone captures(none) %0) unnamed_addr #0 { fence syncscope("singlethread") seq_cst ret i64 0 } attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn "target-cpu"="generic" } !llvm.ident = !{!0} !0 = !{!"rustc version 1.97.0-nightly (f53b654a8 2026-04-30)"} ``` **Error** ``` LLVM ERROR: Cannot select: 0x7fcf7701a1c0: ch = AtomicFence 0x7fcf75718df8, TargetConstant:i64<7>, TargetConstant:i64<0> In function: entrypoint Stack dump: 0. Running pass 'Function Pass Manager' on module 'linked_module'. 1. Running pass 'BPF DAG->DAG Pattern Instruction Selection' on function '@entrypoint' ``` ----- **Fix** This patch lowers single-thread (compiler) fences to `ISD::MEMBARRIER` (no-op) and produces an error for cross-thread (runtime) fences.

@entrypoint

The BPF backend has no instruction-selection pattern for `ISD::ATOMIC_FENCE`, so LLVM IR containing a fence instruction crashes with `Cannot select: AtomicFence...`. **Rust code snippet** ``` #[unsafe(no_mangle)] pub fn entrypoint(_input: *mut u8) -> u64 { core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst); 0 } ``` **LLVM IR** ``` ; ModuleID = 'linked_module' source_filename = "linked_module" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" target triple = "bpfel" ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn define dso_local noundef i64 @entrypoint(ptr noundef readnone captures(none) %0) unnamed_addr #0 { fence syncscope("singlethread") seq_cst ret i64 0 } attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn "target-cpu"="generic" } !llvm.ident = !{!0} !0 = !{!"rustc version 1.97.0-nightly (f53b654a8 2026-04-30)"} ``` **Error** ``` LLVM ERROR: Cannot select: 0x7fcf7701a1c0: ch = AtomicFence 0x7fcf75718df8, TargetConstant:i64<7>, TargetConstant:i64<0> In function: entrypoint Stack dump: 0. Running pass 'Function Pass Manager' on module 'linked_module'. 1. Running pass 'BPF DAG->DAG Pattern Instruction Selection' on function '@entrypoint' ``` ----- **Fix** This patch lowers single-thread (compiler) fences to `ISD::MEMBARRIER` (no-op) and produces an error for cross-thread (runtime) fences.

yonghong-song requested review from 4ast and eddyz87 May 11, 2026 14:38

yonghong-song approved these changes May 11, 2026

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4ast requested changes May 11, 2026

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bidhan-a force-pushed the BPF_compiler_fence branch from ff7569d to 8fb0b19 Compare May 13, 2026 11:16

bidhan-a changed the title ~~[BPF] treat compiler fence as codegen no-op~~ [BPF] Lower ATOMIC_FENCE: real barrier for cross-thread seq_cst, no-op otherwise May 13, 2026

4ast approved these changes May 13, 2026

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eddyz87 reviewed May 13, 2026

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Comment thread llvm/lib/Target/BPF/BPFISelLowering.cpp

bidhan-a force-pushed the BPF_compiler_fence branch 2 times, most recently from 282e5c0 to e3a19d9 Compare May 15, 2026 04:04

[BPF] treat compiler fence as codegen no-op

831c610

bidhan-a force-pushed the BPF_compiler_fence branch from e3a19d9 to 831c610 Compare May 16, 2026 12:44

bidhan-a changed the title ~~[BPF] Lower ATOMIC_FENCE: real barrier for cross-thread seq_cst, no-op otherwise~~ [BPF] treat compiler fence as codegen no-op May 16, 2026

eddyz87 approved these changes May 19, 2026

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yonghong-song merged commit 571b226 into llvm:main May 19, 2026
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bidhan-a mentioned this pull request May 20, 2026

[BPF] treat compiler fence as codegen no-op (#196734) #198730

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