[AArch64][SDAG] Legalise BSWAP for Neon types.#179702
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BSWAP was made legal for these types for GISel in llvm#80036. Making the types legal avoids them being expanded to vector_shuffle before being matched to REVs, and allows half rotations on i16 vectors to be combined to bswap (see llvm#178706).
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@llvm/pr-subscribers-llvm-analysis Author: Ricardo Jesus (rj-jesus) ChangesGlobalISel legalised BSWAP for Neon types in #80036. Legalising the types keeps them from being expanded to vector_shuffle before being matched to REVs, and allows half-rotations on i16 vectors to be combined to bswap (see #178706 (comment)). Full diff: https://github.com/llvm/llvm-project/pull/179702.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 6c0544005e1dd..78c4c77b99b6f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1408,7 +1408,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
- setOperationAction(ISD::BSWAP, VT, Expand);
+ if (VT == MVT::v4i16 || VT == MVT::v8i16 || VT == MVT::v2i32 ||
+ VT == MVT::v4i32 || VT == MVT::v2i64)
+ setOperationAction(ISD::BSWAP, VT, Legal);
+ else
+ setOperationAction(ISD::BSWAP, VT, Expand);
setOperationAction(ISD::CTTZ, VT, Expand);
for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
diff --git a/llvm/test/Analysis/CostModel/AArch64/bswap.ll b/llvm/test/Analysis/CostModel/AArch64/bswap.ll
index 2df508ebe40bc..43b1d252d04ee 100644
--- a/llvm/test/Analysis/CostModel/AArch64/bswap.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/bswap.ll
@@ -44,7 +44,7 @@ define void @neon() {
; CHECK-NEXT: Cost Model: Found costs of 1 for: %v2i64 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> undef)
; CHECK-NEXT: Cost Model: Found costs of 2 for: %v4i64 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> undef)
; CHECK-NEXT: Cost Model: Found costs of 1 for: %v3i32 = call <3 x i32> @llvm.bswap.v3i32(<3 x i32> undef)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:8 Lat:12 SizeLat:12 for: %v4i48 = call <4 x i48> @llvm.bswap.v4i48(<4 x i48> undef)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %v4i48 = call <4 x i48> @llvm.bswap.v4i48(<4 x i48> undef)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%v4i16 = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> undef)
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Member
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@llvm/pr-subscribers-backend-aarch64 Author: Ricardo Jesus (rj-jesus) ChangesGlobalISel legalised BSWAP for Neon types in #80036. Legalising the types keeps them from being expanded to vector_shuffle before being matched to REVs, and allows half-rotations on i16 vectors to be combined to bswap (see #178706 (comment)). Full diff: https://github.com/llvm/llvm-project/pull/179702.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 6c0544005e1dd..78c4c77b99b6f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1408,7 +1408,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
- setOperationAction(ISD::BSWAP, VT, Expand);
+ if (VT == MVT::v4i16 || VT == MVT::v8i16 || VT == MVT::v2i32 ||
+ VT == MVT::v4i32 || VT == MVT::v2i64)
+ setOperationAction(ISD::BSWAP, VT, Legal);
+ else
+ setOperationAction(ISD::BSWAP, VT, Expand);
setOperationAction(ISD::CTTZ, VT, Expand);
for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
diff --git a/llvm/test/Analysis/CostModel/AArch64/bswap.ll b/llvm/test/Analysis/CostModel/AArch64/bswap.ll
index 2df508ebe40bc..43b1d252d04ee 100644
--- a/llvm/test/Analysis/CostModel/AArch64/bswap.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/bswap.ll
@@ -44,7 +44,7 @@ define void @neon() {
; CHECK-NEXT: Cost Model: Found costs of 1 for: %v2i64 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> undef)
; CHECK-NEXT: Cost Model: Found costs of 2 for: %v4i64 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> undef)
; CHECK-NEXT: Cost Model: Found costs of 1 for: %v3i32 = call <3 x i32> @llvm.bswap.v3i32(<3 x i32> undef)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:8 Lat:12 SizeLat:12 for: %v4i48 = call <4 x i48> @llvm.bswap.v4i48(<4 x i48> undef)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %v4i48 = call <4 x i48> @llvm.bswap.v4i48(<4 x i48> undef)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%v4i16 = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> undef)
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🐧 Linux x64 Test Results
Failed Tests(click on a test name to see its output) lldb-apilldb-api.tools/lldb-dap/stopped-events/TestDAP_stopped_events.pyIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
paulwalker-arm
approved these changes
Feb 5, 2026
AlexisPerry
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Feb 6, 2026
GlobalISel legalised BSWAP for Neon types in llvm#80036. Legalising the types keeps them from being expanded to vector_shuffle before being matched to REVs, and allows half-rotations on i16 vectors to be combined to bswap (see llvm#178706 (comment)).
rishabhmadan19
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that referenced
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Feb 9, 2026
GlobalISel legalised BSWAP for Neon types in llvm#80036. Legalising the types keeps them from being expanded to vector_shuffle before being matched to REVs, and allows half-rotations on i16 vectors to be combined to bswap (see llvm#178706 (comment)).
Xinlong-Chen
pushed a commit
to Xinlong-Chen/llvm-project
that referenced
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Feb 12, 2026
GlobalISel legalised BSWAP for Neon types in llvm#80036. Legalising the types keeps them from being expanded to vector_shuffle before being matched to REVs, and allows half-rotations on i16 vectors to be combined to bswap (see llvm#178706 (comment)).
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GlobalISel legalised BSWAP for Neon types in #80036.
Legalising the types keeps them from being expanded to vector_shuffle before being matched to REVs, and allows half-rotations on i16 vectors to be combined to bswap (see #178706 (comment)).