[GlobalISel] add G_ROTL, G_ROTR to computeKnownBits by mooori · Pull Request #166365 · llvm/llvm-project

mooori · 2025-11-04T12:32:56Z

Adresses one of the subtasks of #150515.

The code is ported from SelectionDAG::computeKnownBits and tests are loosely based on AArch64/GlobalISel/knownbits-shl.mir.

github-actions · 2025-11-04T12:33:16Z

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llvmbot · 2025-11-04T12:34:40Z

@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-llvm-globalisel

Author: Moritz Zielke (mooori)

Changes

Adresses one of the subtasks of #150515.

The code is ported from SelectionDAG::computeKnownBits and tests are loosely based on AArch64/GlobalISel/knownbits-shl.mir.

Full diff: https://github.com/llvm/llvm-project/pull/166365.diff

2 Files Affected:

(modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+21)
(added) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir (+270)

diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index d6f23b62519fe..5b45a0d9a506b 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -483,6 +483,27 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
     Known = KnownBits::shl(LHSKnown, RHSKnown);
     break;
   }
+  case TargetOpcode::G_ROTL:
+  case TargetOpcode::G_ROTR: {
+    MachineInstr *AmtOpMI = MRI.getVRegDef(MI.getOperand(2).getReg());
+    if (!AmtOpMI)
+      break;
+    auto MaybeAmtOp = isConstantOrConstantSplatVector(*AmtOpMI, MRI);
+    if (MaybeAmtOp.has_value()) {
+      unsigned Amt = MaybeAmtOp.value().urem(BitWidth);
+
+      Register SrcReg = MI.getOperand(1).getReg();
+      computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
+
+      // Canonicalize to ROTR.
+      if (Opcode == TargetOpcode::G_ROTL && Amt != 0)
+        Amt = BitWidth - Amt;
+
+      Known.Zero = Known.Zero.rotr(Amt);
+      Known.One = Known.One.rotr(Amt);
+    }
+    break;
+  }
   case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_PTRTOINT:
     if (DstTy.isVector())
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir
new file mode 100644
index 0000000000000..d468c84ce899f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir
@@ -0,0 +1,270 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s
+
+---
+name:            Cst
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @Cst
+  ; CHECK-NEXT: %0:_ KnownBits:11100010 SignBits:3
+  ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
+  ; CHECK-NEXT: %2:_ KnownBits:10111000 SignBits:1
+    %0:_(s8) = G_CONSTANT i8 226
+    %1:_(s8) = G_CONSTANT i8 2
+    %2:_(s8) = G_ROTR %0, %1
+...
+---
+name:            CstBig
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CstBig
+  ; CHECK-NEXT: %0:_ KnownBits:11111001 SignBits:5
+  ; CHECK-NEXT: %1:_ KnownBits:00000110 SignBits:5
+  ; CHECK-NEXT: %2:_ KnownBits:11100111 SignBits:3
+    %0:_(s8) = G_CONSTANT i8 249
+    %1:_(s8) = G_CONSTANT i8 6
+    %2:_(s8) = G_ROTR %0, %1
+...
+---
+name:            CstSext
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CstSext
+  ; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+  ; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5
+  ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5
+  ; CHECK-NEXT: %4:_ KnownBits:10001111 SignBits:1
+    %0:_(s8) = G_CONSTANT i8 129
+    %1:_(s8) = G_CONSTANT i8 4
+    %2:_(s8) = G_ASHR %0, %1
+    %3:_(s8) = G_CONSTANT i8 4
+    %4:_(s8) = G_ROTR %2, %3
+...
+---
+name:            CstSextBig
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CstSextBig
+  ; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+  ; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5
+  ; CHECK-NEXT: %3:_ KnownBits:00000110 SignBits:5
+  ; CHECK-NEXT: %4:_ KnownBits:11100011 SignBits:3
+    %0:_(s8) = G_CONSTANT i8 129
+    %1:_(s8) = G_CONSTANT i8 4
+    %2:_(s8) = G_ASHR %0, %1
+    %3:_(s8) = G_CONSTANT i8 6
+    %4:_(s8) = G_ROTR %2, %3
+...
+---
+name:            ScalarVar
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @ScalarVar
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+    %0:_(s8) = COPY $b0
+    %1:_(s8) = COPY $b1
+    %2:_(s8) = G_ROTR %0, %1
+...
+---
+name:            ScalarCst
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @ScalarCst
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
+  ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+    %0:_(s8) = COPY $b0
+    %1:_(s8) = G_CONSTANT i8 3
+    %2:_(s8) = G_ROTR %0, %1
+...
+---
+name:            VectorVar
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorVar
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+    %0:_(<4 x s16>) = COPY $d0
+    %1:_(<4 x s16>) = COPY $d1
+    %2:_(<4 x s16>) = G_ROTR %0, %1
+...
+---
+name:            VectorSimple
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorSimple
+  ; CHECK-NEXT: %0:_ KnownBits:0000000000010011 SignBits:11
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000010011 SignBits:11
+  ; CHECK-NEXT: %3:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %4:_ KnownBits:0110000000000010 SignBits:1
+    %0:_(s16) = G_CONSTANT i16 19
+    %1:_(s16) = G_CONSTANT i16 3
+    %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+    %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+    %4:_(<4 x s16>) = G_ROTR %2, %3
+...
+---
+name:            VectorCst
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorCst
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+    %0:_(<4 x s16>) = COPY $d0
+    %1:_(s16) = G_CONSTANT i16 3
+    %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+    %3:_(<4 x s16>) = G_ROTR %0, %2
+...
+---
+name:            VectorCst36
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorCst36
+  ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13
+  ; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13
+  ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+    %0:_(s16) = G_CONSTANT i16 3
+    %1:_(s16) = G_CONSTANT i16 6
+    %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+    %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+    %4:_(<4 x s16>) = G_ROTR %2, %3
+...
+
+---
+name:            VectorCst3unknown
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorCst3unknown
+  ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+    %0:_(<4 x s16>) = COPY $d0
+    %1:_(s16) = COPY $h0
+    %2:_(s16) = G_CONSTANT i16 3
+    %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+    %4:_(<4 x s16>) = G_ROTR %0, %3
+...
+---
+name:            VectorSext
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorSext
+  ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
+  ; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11
+  ; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11
+  ; CHECK-NEXT: %3:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %4:_ KnownBits:0000000000000110 SignBits:13
+  ; CHECK-NEXT: %5:_ KnownBits:0000000000000?1? SignBits:13
+  ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:1
+    %0:_(s8) = G_CONSTANT i8 238
+    %1:_(s16) = G_SEXT %0(s8)
+    %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+    %3:_(s16) = G_CONSTANT i16 3
+    %4:_(s16) = G_CONSTANT i16 6
+    %5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
+    %6:_(<4 x s16>) = G_ROTR %2, %5
+...
+---
+name:            VectorSextBig
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @VectorSextBig
+  ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
+  ; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11
+  ; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11
+  ; CHECK-NEXT: %3:_ KnownBits:0000000000001000 SignBits:12
+  ; CHECK-NEXT: %4:_ KnownBits:0000000000001001 SignBits:12
+  ; CHECK-NEXT: %5:_ KnownBits:000000000000100? SignBits:12
+  ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:1
+    %0:_(s8) = G_CONSTANT i8 238
+    %1:_(s16) = G_SEXT %0(s8)
+    %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+    %3:_(s16) = G_CONSTANT i16 8
+    %4:_(s16) = G_CONSTANT i16 9
+    %5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
+    %6:_(<4 x s16>) = G_ROTR %2, %5
+...
+---
+name:            ROTRless
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @ROTRless
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+    %0:_(s8) = COPY $b0
+    %1:_(s16) = G_SEXT %0(s8)
+    %2:_(s16) = G_CONSTANT i16 3
+    %3:_(s16) = G_ROTR %1, %2
+...
+---
+name:            ROTReq
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @ROTReq
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000001000 SignBits:12
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+    %0:_(s8) = COPY $b0
+    %1:_(s16) = G_SEXT %0(s8)
+    %2:_(s16) = G_CONSTANT i16 8
+    %3:_(s16) = G_ROTR %1, %2
+...
+---
+name:            ROTRmore
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @ROTRmore
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
+  ; CHECK-NEXT: %2:_ KnownBits:0000000000001101 SignBits:12
+  ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+    %0:_(s8) = COPY $b0
+    %1:_(s16) = G_SEXT %0(s8)
+    %2:_(s16) = G_CONSTANT i16 13
+    %3:_(s16) = G_ROTR %1, %2
+...
+---
+name:            SignBitsThroughZext
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @SignBitsThroughZext
+  ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
+  ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:4
+  ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
+  ; CHECK-NEXT: %4:_ KnownBits:0000000000001000 SignBits:12
+  ; CHECK-NEXT: %5:_ KnownBits:????????00000000 SignBits:1
+    %0:_(s8) = COPY $b0
+    %1:_(s16) = G_CONSTANT i16 3
+    %2:_(s8) = G_ASHR %0, %1
+    %3:_(s16) = G_ZEXT %2
+    %4:_(s16) = G_CONSTANT i16 8
+    %5:_(s16) = G_ROTR %3, %4
+...
+---
+name:            ROTRCanonicalize
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @ROTRCanonicalize
+  ; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3
+  ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
+  ; CHECK-NEXT: %2:_ KnownBits:10000011 SignBits:1
+    %0:_(s8) = G_CONSTANT i8 224
+    %1:_(s8) = G_CONSTANT i8 2
+    %2:_(s8) = G_ROTL %0, %1
+...

jayfoad · 2025-11-05T11:05:11Z

+      computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
+
+      // Canonicalize to ROTR.
+      if (Opcode == TargetOpcode::G_ROTL && Amt != 0)


Simpler:

Suggested change

if (Opcode == TargetOpcode::G_ROTL && Amt != 0)

if (Opcode == TargetOpcode::G_ROTL)

The DAG version has the 0 check

arsenm · 2025-11-05T15:56:23Z

+    unsigned Amt = MaybeAmtOp->urem(BitWidth);
+
+    Register SrcReg = MI.getOperand(1).getReg();
+    computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
+
+    // Canonicalize to ROTR.
+    if (Opcode == TargetOpcode::G_ROTL)


Suggested change

unsigned Amt = MaybeAmtOp->urem(BitWidth);

Register SrcReg = MI.getOperand(1).getReg();

computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);

// Canonicalize to ROTR.

if (Opcode == TargetOpcode::G_ROTL)

Register SrcReg = MI.getOperand(1).getReg();

computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);

unsigned Amt = MaybeAmtOp->urem(BitWidth);

// Canonicalize to ROTR.

if (Opcode == TargetOpcode::G_ROTL)

mooori · 2025-11-05T19:59:05Z

Could we run the CI workflows? I don't have permission to approve them.

mooori · 2025-11-06T11:20:07Z

Is it possible to view details regarding the buildkite failures? Following the links from below panel I can only see empty logs (e.g. here).

github-actions · 2026-02-07T15:32:27Z

@mooori Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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Adresses one of the subtasks of llvm#150515. The code is ported from `SelectionDAG::computeKnownBits` and tests are loosely based on `AArch64/GlobalISel/knownbits-shl.mir`.

[GlobalISel] add G_ROTL, G_ROTR to computeKnownBits

491b20b

mooori marked this pull request as ready for review November 4, 2025 12:34

llvmbot added backend:AArch64 llvm:globalisel labels Nov 4, 2025

arsenm reviewed Nov 4, 2025

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Comment thread llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp Outdated

Comment thread llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp Outdated

Comment thread llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp Outdated

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mooori added 2 commits November 5, 2025 13:30

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Merge remote-tracking branch 'upstream/main' into gisel-knownbits-rotlr

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mooori requested review from arsenm and jayfoad November 5, 2025 13:22

arsenm approved these changes Nov 5, 2025

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davemgreen mentioned this pull request Nov 5, 2025

[GlobalISel] Port known-bit and known-sign-bits for all operations #150515

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mooori added 2 commits November 5, 2025 20:23

Address review comment

c57ff7a

Merge remote-tracking branch 'upstream/main' into gisel-knownbits-rotlr

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Merge branch 'main' into gisel-knownbits-rotlr

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arsenm enabled auto-merge (squash) February 7, 2026 15:02

arsenm merged commit b0cc73d into llvm:main Feb 7, 2026
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[GlobalISel] add G_ROTL, G_ROTR to computeKnownBits#166365

[GlobalISel] add G_ROTL, G_ROTR to computeKnownBits#166365
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	if (Opcode == TargetOpcode::G_ROTL && Amt != 0)
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