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Hexagon and fix the isel-buildvector-v2f16.ll assertion
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@llvm/pr-subscribers-backend-hexagon Author: Abinaya Saravanan (quic-asaravan) ChangesFull diff: https://github.com/llvm/llvm-project/pull/130977.diff 3 Files Affected:
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index aaa9c65c1e07e..4df88b3a8abd7 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -362,6 +362,7 @@ class HexagonTargetLowering : public TargetLowering {
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
return AtomicExpansionKind::LLSC;
}
+ bool softPromoteHalfType() const override { return true; }
private:
void initializeHVXLowering();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index f77bda3138354..de2bac6905530 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1618,17 +1618,6 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG)
for (unsigned i = 0; i != Size; ++i)
Ops.push_back(Op.getOperand(i));
- // First, split the BUILD_VECTOR for vector pairs. We could generate
- // some pairs directly (via splat), but splats should be generated
- // by the combiner prior to getting here.
- if (VecTy.getSizeInBits() == 16*Subtarget.getVectorLength()) {
- ArrayRef<SDValue> A(Ops);
- MVT SingleTy = typeSplit(VecTy).first;
- SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG);
- SDValue V1 = buildHvxVectorReg(A.drop_front(Size/2), dl, SingleTy, DAG);
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
- }
-
if (VecTy.getVectorElementType() == MVT::i1)
return buildHvxVectorPred(Ops, dl, VecTy, DAG);
@@ -1645,6 +1634,17 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG)
return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0);
}
+ // First, split the BUILD_VECTOR for vector pairs. We could generate
+ // some pairs directly (via splat), but splats should be generated
+ // by the combiner prior to getting here.
+ if (VecTy.getSizeInBits() == 16 * Subtarget.getVectorLength()) {
+ ArrayRef<SDValue> A(Ops);
+ MVT SingleTy = typeSplit(VecTy).first;
+ SDValue V0 = buildHvxVectorReg(A.take_front(Size / 2), dl, SingleTy, DAG);
+ SDValue V1 = buildHvxVectorReg(A.drop_front(Size / 2), dl, SingleTy, DAG);
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
+ }
+
return buildHvxVectorReg(Ops, dl, VecTy, DAG);
}
diff --git a/llvm/test/CodeGen/Hexagon/fp16-promote.ll b/llvm/test/CodeGen/Hexagon/fp16-promote.ll
new file mode 100644
index 0000000000000..1ef0a133ce30a
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fp16-promote.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define half @freeze_half_undef() nounwind {
+; CHECK-LABEL: freeze_half_undef:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: call __truncsfhf2
+; CHECK-NEXT: r0 = #0
+; CHECK-NEXT: allocframe(#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: call __extendhfsf2
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: call __truncsfhf2
+; CHECK-NEXT: r0 = sfadd(r0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT: }
+ %y1 = freeze half undef
+ %t1 = fadd half %y1, %y1
+ ret half %t1
+}
+
+define half @freeze_half_poison(half %maybe.poison) {
+; CHECK-LABEL: freeze_half_poison:
+; CHECK: // %bb.0:
+; CHECK: {
+; CHECK-NEXT: call __extendhfsf2
+; CHECK-NEXT: allocframe(r29,#0):raw
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: call __truncsfhf2
+; CHECK-NEXT: r0 = sfadd(r0,r0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT: }
+ %y1 = freeze half %maybe.poison
+ %t1 = fadd half %y1, %y1
+ ret half %t1
+}
|
Contributor
Author
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This fixes #117337. |
Contributor
Author
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@iajbar @androm3da Can you please review this ? |
iajbar
approved these changes
Mar 12, 2025
Contributor
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Fixes #107791 |
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alexrp
reviewed
Mar 12, 2025
| shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override { | ||
| return AtomicExpansionKind::LLSC; | ||
| } | ||
| bool softPromoteHalfType() const override { return true; } |
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I suppose this is technically an ABI change, thus precluding a backport to 20.1.1, right?
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@tstellar is this kind of change one that prevents backporting? Or requires a 20.2.x?
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Mar 25, 2025
…xagon and fix the isel-buildvector-v2f16.ll assertion (llvm#130977) (cherry picked from commit 9c65e6a)
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LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here.
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LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually done in LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here.
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LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here.
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Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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Rollup merge of #144987 - tgross35:llvm21-f16-f128, r=nikic Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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Enable f16 and f128 on targets that were fixed in LLVM21 LLVM21 fixed the new float types on a number of targets: * SystemZ gained f16 support llvm/llvm-project#109164 * Hexagon now uses soft f16 to avoid recursion bugs llvm/llvm-project#130977 * Mips now correctly handles f128 (actually since LLVM20) llvm/llvm-project#117525 * f128 is now correctly aligned when passing the stack on x86 llvm/llvm-project#138092 Thus, enable the types on relevant targets for LLVM > 21.0.0. NVPTX also gained handling of f128 as a storage type, but it lacks support for basic math operations so is still disabled here. try-job: dist-i586-gnu-i586-i686-musl try-job: dist-i686-linux try-job: dist-i686-msvc try-job: dist-s390x-linux try-job: dist-various-1 try-job: dist-various-2 try-job: dist-x86_64-linux try-job: i686-gnu-1 try-job: i686-gnu-2 try-job: i686-msvc-1 try-job: i686-msvc-2 try-job: test-various
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