ggml-cpu:add RISC-V vector intrinsic support for silu and cvar operat…#17227
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slaren merged 1 commit intoggml-org:masterfrom Nov 13, 2025
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ggml-cpu:add RISC-V vector intrinsic support for silu and cvar operat…#17227slaren merged 1 commit intoggml-org:masterfrom
slaren merged 1 commit intoggml-org:masterfrom
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…ions Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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…ations (ggml-org#17227) Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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…ations (#17227) Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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This commit adds RISC-V vector intrinsic implementations for the ggml_vec_silu_f32 and ggml_vec_cvar_f32 functions, similar to the existing optimizations for other architectures (AVX, SSE, NEON, SVE).