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[pulse_counter] Fix compilation on ESP32-C6/C5/H2/P4#14070

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bdraco merged 1 commit intodevfrom
fix-pulse-counter-c6-compile
Feb 19, 2026
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[pulse_counter] Fix compilation on ESP32-C6/C5/H2/P4#14070
bdraco merged 1 commit intodevfrom
fix-pulse-counter-c6-compile

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@bdraco bdraco commented Feb 19, 2026

What does this implement/fix?

Fixes compilation error on ESP32-C6 (and C5, H2, P4) where SOC_MOD_CLK_APB does not exist in the soc_module_clk_t enum. These newer variants removed the APB clock enum entry — C6 has SOC_MOD_CLK_PLL_F80M instead.

#13908 replaced esp_clk_apb_freq() with esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_APB, ...) for the PCNT glitch filter calculation. While the esp_clk_tree migration was correct for the RMT components (using RMT_CLK_SRC_DEFAULT), PCNT has no equivalent portable clock source enum.

This reverts the pulse_counter portion back to esp_clk_apb_freq() from esp_private/esp_clk.h, which is the approach introduced in #13904. Sorry @swoboda1337 — I shouldn't have pushed back on the private API usage in #13908. It turns out esp_clk_apb_freq() is what the ESP-IDF PCNT driver itself uses internally for glitch filter calculation (pulse_cnt.c:404), it works correctly on all ESP32 variants, and there's simply no public API equivalent. It's what we're stuck with until Espressif provides one.

Types of changes

  • Bugfix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)
  • Developer breaking change (an API change that could break external components)
  • Code quality improvements to existing code or addition of tests
  • Other

Related issue or feature (if applicable):

Pull request in esphome-docs with documentation (if applicable):

  • N/A

Test Environment

  • ESP32
  • ESP32 IDF
  • ESP8266
  • RP2040
  • BK72xx
  • RTL87xx
  • LN882x
  • nRF52840

Example entry for config.yaml:

sensor:
  - platform: pulse_counter
    pin: GPIO18
    name: "Pulse Counter"

Checklist:

  • The code change is tested and works locally.
  • Tests have been added to verify that the new code works (under tests/ folder).

If user exposed functionality or configuration variables are added/changed:

SOC_MOD_CLK_APB does not exist in the soc_module_clk_t enum on
ESP32-C6, C5, H2, and P4 variants. Revert to esp_clk_apb_freq()
which works on all variants and is the same function the ESP-IDF
PCNT driver uses internally for glitch filter calculation.
Copilot AI review requested due to automatic review settings February 19, 2026 00:40
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To use the changes from this PR as an external component, add the following to your ESPHome configuration YAML file:

external_components:
  - source: github://pr#14070
    components: [pulse_counter]
    refresh: 1h

(Added by the PR bot)

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codecov-commenter commented Feb 19, 2026

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 74.11%. Comparing base (bd055e7) to head (9dd62b8).

Additional details and impacted files
@@           Coverage Diff           @@
##              dev   #14070   +/-   ##
=======================================
  Coverage   74.11%   74.11%           
=======================================
  Files          55       55           
  Lines       11589    11589           
  Branches     1578     1578           
=======================================
  Hits         8589     8589           
  Misses       2598     2598           
  Partials      402      402           

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

🚀 New features to boost your workflow:
  • ❄️ Test Analytics: Detect flaky tests, report on failures, and find test suite problems.

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Memory Impact Analysis

Components: pulse_counter
Platform: esp8266-ard

Metric Target Branch This PR Change
RAM 28,576 bytes 28,576 bytes ➡️ +0 bytes (0.00%)
Flash 281,659 bytes 281,659 bytes ➡️ +0 bytes (0.00%)

Note: This analysis measures static RAM and Flash usage only (compile-time allocation).
Dynamic memory (heap) cannot be measured automatically.
⚠️ You must test this PR on a real device to measure free heap and ensure no runtime memory issues.

This analysis runs automatically when components change. Memory usage is measured from a representative test configuration.

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Pull request overview

Fixes ESP32-C6/C5/H2/P4 build failures in pulse_counter by avoiding use of the removed SOC_MOD_CLK_APB clock enum when computing the PCNT glitch filter timing.

Changes:

  • Replace esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_APB, ...) with esp_clk_apb_freq() for APB frequency lookup in the glitch filter calculation.
  • Switch the included clock header from esp_clk_tree.h to esp_private/esp_clk.h to access esp_clk_apb_freq().

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tested, works

@bdraco bdraco merged commit 565443b into dev Feb 19, 2026
47 checks passed
@bdraco bdraco deleted the fix-pulse-counter-c6-compile branch February 19, 2026 01:08
@swoboda1337 swoboda1337 mentioned this pull request Feb 20, 2026
@github-actions github-actions bot locked and limited conversation to collaborators Feb 21, 2026
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Compile error with pulse_counter

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