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@copilot please evaluate and address the feedback

Code Review: Atanh Vectorization

❌ Bug: Vector256.Atanh(Vector256<float>) unconditionally uses Vector512 without availability check

File: src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Vector256.cs (lines 877–890)
Severity: High

Vector256.Atanh(Vector256<float>) unconditionally instantiates VectorMath.AtanhSingle with Vector512<double> type parameters when IsHardwareAccelerated is true, without first checking Vector512.IsHardwareAccelerated. On systems with AVX2 but no AVX-512 (the vast majority of deployed x86-64 CPUs), every Vector512 operation inside the math kernel will be software-emulated as pairs of Vector256 operations, defeating the purpose of vectorization.

Current code:

public static Vector256<float> Atanh(Vector256<float> vector)
{
    if (IsHardwareAccelerated)
    {
        // ⚠️ Always uses Vector512 — no availability check
        return VectorMath.AtanhSingle<Vector256<float>, Vector256<int>, Vector256<uint>,
            Vector512<double>, Vector512<long>, Vector512<ulong>>(vector);
    }
    ...
}

Every other Vector256 single-precision math function in the same file guards on Vector512.IsHardwareAccelerated:

Note that the PR's own sibling methods Vector64.Atanh(float) (checks Vector128.IsHardwareAccelerated) and Vector128.Atanh(float) (checks Vector256.IsHardwareAccelerated) correctly follow the pattern — only the Vector256 case was missed.

Suggested fix: Add the guard and provide a Vector256<double> fallback, matching the Asin pattern directly above:

if (IsHardwareAccelerated)
{
    if (Vector512.IsHardwareAccelerated)
    {
        return VectorMath.AtanhSingle<Vector256<float>, Vector256<int>, Vector256<uint>,
            Vector512<double>, Vector512<long>, Vector512<ulong>>(vector);
    }
    else
    {
        return VectorMath.AtanhSingle<Vector256<float>, Vector256<int>, Vector256<uint>,
            Vector256<double>, Vector256<long>, Vector256<ulong>>(vector);
    }
}

Everything else reviewed looks correct:

• ✅ AtanhDouble / AtanhSingleCoreDouble numerical formulas, sign/infinity/NaN handling, and ConditionalSelect ordering
• ✅ log(1+ratio) instead of log1p(ratio) is safe since the large path guarantees 1+ratio ≥ 3
• ✅ Polynomial coefficients sourced from AMD AOCL-libm
• ✅ Ref assembly, Vector64/128/512 entry points, and test tolerance updates

Generated by Code Review for issue #126420 · ◷

@copilot please evaluate and address the feedback

Addressed both feedback items in 046a5e3:

1. Vector256.Atanh(float) IsHardwareAccelerated check: Added the Vector512.IsHardwareAccelerated branch (matching the pattern used by Asin/Cos/Exp) so it falls back to Vector256<double> when Vector512 isn't hardware-accelerated.

2. Unit tests: Added AtanhDoubleTest and AtanhSingleTest to all four test files (Vector64/128/256/512Tests.cs) with test data in GenericMathTestMemberData covering NaN, ±0, ±1 (→ ±Infinity), |x|>1 (→ NaN), and standard mathematical constants. All 13,096 tests pass.