erasure-code: Increase SIMD_ALIGN from 32 to 64#60246
erasure-code: Increase SIMD_ALIGN from 32 to 64#60246SrinivasaBharath merged 1 commit intoceph:mainfrom
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Fixes: https://tracker.ceph.com/issues/61573 Signed-off-by: Jamie Pryde <jamiepry@uk.ibm.com>
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jenkins test make check arm64 |
markhpc
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LGTM assuming there are no weird corner cases it breaks!
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This pull request has been automatically marked as stale because it has not had any activity for 60 days. It will be closed if no further activity occurs for another 30 days. |
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@yuriw Any idea if this one passed testing? Thanks! |
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Hey @jamiepryde and @markhpc, apologies for the delay on this one. I see an erasure code timeout would be good to confirm isn't a regression before moving foward: Since the failure is a bit ambiguous, I am going to retest it along with #59679, for which I also identified a timeout on a test with the new isa profile. Doing an isolated retest will give us a better idea if this is a regression. Testing ref: https://tracker.ceph.com/issues/68795 |




Fixes: https://tracker.ceph.com/issues/61573
We want the buffers used for erasure coding to be 64-byte aligned. This should ensure that they fit a single 64 byte cache line for AVX512 instructions. If the buffers are misaligned then we can see a reduction in performance as the CPU has to do extra loads from memory.
The testing in the tracker does show a performance gain using 64-byte alignment. I wasn't able to see any improvement in my own testing, but this could be down to the CPU I used (Xeon Gold 6336Y).
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