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Splat WIP#2

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bnjbvr wants to merge 25 commits intomasterfrom
abrown-add-splat
Closed

Splat WIP#2
bnjbvr wants to merge 25 commits intomasterfrom
abrown-add-splat

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@bnjbvr
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@bnjbvr bnjbvr commented Jul 2, 2019

@abrown Here are my changes. I am bit surprised by the code generated to legalize splat into bitcast+pshufd in legalize-x86.rs, but it seems to work.

This is almost working! I suspect the remaining part is that we want to define an encoding for bitcast.i32x4 in the x86 meta encodings file.

bnjbvr and others added 25 commits July 2, 2019 18:30
… checks;

Also add the instruction format name in format predicates, since they're
going to be used when generating encodings.
This is a map with facilities to insert a default value when the
searched key has no entry yet.
The latter helps deduplicating predicates during encodings and recipes
construction.
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
KILL THE SNAKE WITH FIRE.
This assert was added when porting legalization from Python to Rust and
doesn't hold when we have derived type variables.
@abrown abrown mentioned this pull request Jul 2, 2019
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bnjbvr commented Jul 4, 2019

I'll close my PR now, and will cherry-pick the 3 commits related to meta-code, so they get reviewed on the original Cranelift repo. Feel free to take over interesting content from other commits, if you'd like to, @abrown !

@bnjbvr bnjbvr closed this Jul 4, 2019
abrown added a commit to abrown/cranelift that referenced this pull request Jul 11, 2019
Contains fixes from @bnjbvr to codegen as a part of bnjbvr#2; necessary for SIMD features to work
sunfishcode pushed a commit to bytecodealliance/cranelift that referenced this pull request Jul 17, 2019
Contains fixes from @bnjbvr to codegen as a part of bnjbvr#2; necessary for SIMD features to work
@bnjbvr bnjbvr deleted the abrown-add-splat branch September 11, 2019 11:59
bnjbvr pushed a commit that referenced this pull request Oct 1, 2019
The x86 ISA has (at least) two encodings for PEXTRW:
 1. in the SSE2 opcode (66 0f c5) the XMM operand uses r/m and the GPR operand uses reg
 2. in the SSE4.1 opcode (66 0f 3a 15) the XMM operand uses reg and the GPR operand uses r/m

This changes the 16-bit x86_pextr encoding from 1 to 2 to match the other PEXTR* implementations (all #2 style).
bnjbvr pushed a commit that referenced this pull request Feb 26, 2020
arkpar pushed a commit to paritytech/wasmtime that referenced this pull request Mar 4, 2020
Contains fixes from @bnjbvr to codegen as a part of bnjbvr/cranelift#2; necessary for SIMD features to work
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