Avoid mixing SSE and AVX in XTS-mode AVX512 implementation#2140
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torben-hansen merged 2 commits intoaws:mainfrom Jan 27, 2025
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Avoid mixing SSE and AVX in XTS-mode AVX512 implementation#2140torben-hansen merged 2 commits intoaws:mainfrom
torben-hansen merged 2 commits intoaws:mainfrom
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Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #2140 +/- ##
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Coverage 78.95% 78.95%
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Files 610 610
Lines 105293 105293
Branches 14919 14920 +1
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+ Hits 83136 83138 +2
+ Misses 21505 21502 -3
- Partials 652 653 +1 ☔ View full report in Codecov by Sentry. |
andrewhop
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nebeid
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Excellent find, @torben-hansen and thanks @andrewhop for reporting.
manastasova
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A bimodal performance occurred in the XTS encrypt AVX512 implementation. We have observed more than 80% drop in performance. This is caused by mixing SSE and AVX instructions in the AVX512 implementation. For a subset of input lengths, the code path contained a single move movdqa, an SSE instruction. Use vmovdqa instead.
nebeid
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Apr 8, 2025
A bimodal performance occurred in the XTS encrypt AVX512 implementation. We have observed more than 80% drop in performance. This is caused by mixing SSE and AVX instructions in the AVX512 implementation. For a subset of input lengths, the code path contained a single move movdqa, an SSE instruction. Use vmovdqa instead.
nebeid
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Apr 8, 2025
A bimodal performance occurred in the XTS encrypt AVX512 implementation. We have observed more than 80% drop in performance. This is caused by mixing SSE and AVX instructions in the AVX512 implementation. For a subset of input lengths, the code path contained a single move movdqa, an SSE instruction. Use vmovdqa instead. (cherry picked from commit 37c2b5e)
nebeid
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Apr 22, 2025
…lace SSE instructions that degraded performance for certain input lengths (#2319) Original commits: a39439b and 37c2b5e This is a follow-up to #2228 where an out-of-bound (OOB) read was fixed in the AVX512 implementation of AES-XTS and more tests were added. This cherry-picks: - further hardening tests on checking pre-bound reads #2286 - a fix to a performance glitch on a code path that had an SSE instruction instead of an AVX512 one which was triggered by certain input lengths. #2140 By submitting this pull request, I confirm that my contribution is made under the terms of the Apache 2.0 license and the ISC license.
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Issues:
P192842055
Description of changes:
Define the set
S = [i*128+80,i*128+80+15], i=1,2,3,...,. The set of inputs with lengths fromS, on the XTS encrypt path using the AVX512 implementation, a bimodal performance occurred. We have observed more than 80% drop in performance.The graph depicts AWS-LC (blue) and AWS-LC-FIPS-2024 (orange), showing the pattern.
This is caused by mixing SSE and AVX instructions in the AVX512 implementation. In particular, for lengths in
S, the pathL_remaining_num_blocks_is_5_is taken. This path contains a single movemovdqa, an SSE instruction:It's perhaps a less known fact that mixing SSE and AVX instruction can lead to severe performance issues. See e.g. Agner Fog's manual Section 9.12 "Transitions between VEX and non-VEX modes" (at time of writing page 132 in https://www.agner.org/optimize/microarchitecture.pdf):
That appears to be true on our test CPU (Sapphire Rapids) from the c7i instance family. Although, page Section 12.10 in Agner's does state:
Sapphire Rapids is not Ice Lake, but is newer though. So, that's slightly confusing. Nonetheless, to recover performance, a fix should simply be to use the VEX instruction instead of the non-VEX i.e.
vmovdqa.Before:
After:
By submitting this pull request, I confirm that my contribution is made under the terms of the Apache 2.0 license and the ISC license.