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mshinwellmshinwell
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Revert bswap PRs (480 and 482) (oxcaml#501)
1 parent e2d8ed6 commit 52cd50e

14 files changed

Lines changed: 59 additions & 99 deletions

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‎backend/amd64/arch.ml‎

Lines changed: 5 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,6 @@ type prefetch_info = {
7373
addr: addressing_mode;
7474
}
7575

76-
type bswap_bitwidth = Sixteen | Thirtytwo | Sixtyfour
77-
7876
type rounding_mode = Half_to_even | Down | Up | Towards_zero | Current
7977

8078
type specific_operation =
@@ -84,7 +82,7 @@ type specific_operation =
8482
| Ioffset_loc of int * addressing_mode (* Add a constant to a location *)
8583
| Ifloatarithmem of float_operation * addressing_mode
8684
(* Float arith operation with memory *)
87-
| Ibswap of { bitwidth: bswap_bitwidth; } (* endianness conversion *)
85+
| Ibswap of int (* endianness conversion *)
8886
| Isqrtf (* Float square root *)
8987
| Ifloatsqrtf of addressing_mode (* Float square root from memory *)
9088
| Ifloat_iround (* Rounds a [float] to an [int64]
@@ -158,11 +156,6 @@ let string_of_rounding_mode = function
158156
| Towards_zero -> "truncate"
159157
| Current -> "current"
160158

161-
let int_of_bswap_bitwidth = function
162-
| Sixteen -> 16
163-
| Thirtytwo -> 32
164-
| Sixtyfour -> 64
165-
166159
let print_addressing printreg addr ppf arg =
167160
match addr with
168161
| Ibased(s, 0) ->
@@ -211,8 +204,8 @@ let print_specific_operation printreg op ppf arg =
211204
fprintf ppf "%a %s float64[%a]" printreg arg.(0) (op_name op)
212205
(print_addressing printreg addr)
213206
(Array.sub arg 1 (Array.length arg - 1))
214-
| Ibswap { bitwidth } ->
215-
fprintf ppf "bswap_%i %a" (int_of_bswap_bitwidth bitwidth) printreg arg.(0)
207+
| Ibswap i ->
208+
fprintf ppf "bswap_%i %a" i printreg arg.(0)
216209
| Isextend32 ->
217210
fprintf ppf "sextend32 %a" printreg arg.(0)
218211
| Izextend32 ->
@@ -303,8 +296,8 @@ let equal_specific_operation left right =
303296
Int.equal x y && equal_addressing_mode x' y'
304297
| Ifloatarithmem (x, x'), Ifloatarithmem (y, y') ->
305298
equal_float_operation x y && equal_addressing_mode x' y'
306-
| Ibswap { bitwidth = left }, Ibswap { bitwidth = right } ->
307-
Int.equal (int_of_bswap_bitwidth left) (int_of_bswap_bitwidth right)
299+
| Ibswap left, Ibswap right ->
300+
Int.equal left right
308301
| Isqrtf, Isqrtf ->
309302
true
310303
| Ifloatsqrtf left, Ifloatsqrtf right ->

‎backend/amd64/emit.mlp‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -886,13 +886,16 @@ let emit_instr fallthrough i =
886886
I.add (int n) (addressing addr QWORD i 0)
887887
| Lop(Ispecific(Ifloatarithmem(op, addr))) ->
888888
instr_for_floatarithmem op (addressing addr REAL8 i 1) (res i 0)
889-
| Lop(Ispecific(Ibswap { bitwidth = Sixteen })) ->
889+
| Lop(Ispecific(Ibswap 16)) ->
890890
I.xchg ah al;
891891
I.movzx (res16 i 0) (res i 0)
892-
| Lop(Ispecific(Ibswap { bitwidth = Thirtytwo })) ->
892+
| Lop(Ispecific(Ibswap 32)) ->
893893
I.bswap (res32 i 0);
894-
| Lop(Ispecific(Ibswap { bitwidth = Sixtyfour })) ->
894+
I.movsxd (res32 i 0) (res i 0)
895+
| Lop(Ispecific(Ibswap 64)) ->
895896
I.bswap (res i 0)
897+
| Lop(Ispecific(Ibswap _)) ->
898+
assert false
896899
| Lop(Ispecific Isqrtf) ->
897900
if arg i 0 <> res i 0 then
898901
I.xorpd (res i 0) (res i 0); (* avoid partial register stall *)

‎backend/amd64/proc.ml‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,6 @@ let operation_supported = function
458458
| Capply _ | Cextcall _ | Cload _ | Calloc _ | Cstore _
459459
| Caddi | Csubi | Cmuli | Cmulhi _ | Cdivi | Cmodi
460460
| Cand | Cor | Cxor | Clsl | Clsr | Casr
461-
| Cbswap _
462461
| Cclz _ | Cctz _
463462
| Ccmpi _ | Caddv | Cadda | Ccmpa _
464463
| Cnegf | Cabsf | Caddf | Csubf | Cmulf | Cdivf

‎backend/amd64/selection.ml‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,13 @@ let pseudoregs_for_operation op arg res =
9696
(* One-address unary operations: arg.(0) and res.(0) must be the same *)
9797
| Iintop_imm((Iadd|Isub|Imul|Iand|Ior|Ixor|Ilsl|Ilsr|Iasr), _)
9898
| Iabsf | Inegf
99-
| Ispecific(Ibswap { bitwidth = (Thirtytwo | Sixtyfour) }) ->
99+
| Ispecific(Ibswap (32|64)) ->
100100
(res, res)
101101
(* For xchg, args must be a register allowing access to high 8 bit register
102102
(rax, rbx, rcx or rdx). Keep it simple, just force the argument in rax. *)
103-
| Ispecific(Ibswap { bitwidth = Sixteen }) ->
103+
| Ispecific(Ibswap 16) ->
104104
([| rax |], [| rax |])
105+
| Ispecific (Ibswap _) -> assert false
105106
(* For imulh, first arg must be in rax, rax is clobbered, and result is in
106107
rdx. *)
107108
| Iintop(Imulh _) ->
@@ -165,12 +166,6 @@ let select_locality (l : Cmm.prefetch_temporal_locality_hint)
165166
| Moderate -> Moderate
166167
| High -> High
167168

168-
let select_bitwidth : Cmm.bswap_bitwidth -> Arch.bswap_bitwidth =
169-
function
170-
| Sixteen -> Sixteen
171-
| Thirtytwo -> Thirtytwo
172-
| Sixtyfour -> Sixtyfour
173-
174169
let one_arg name args =
175170
match args with
176171
| [arg] -> arg
@@ -180,7 +175,8 @@ let one_arg name args =
180175
(* If you update [inline_ops], you may need to update [is_simple_expr] and/or
181176
[effects_of], below. *)
182177
let inline_ops =
183-
[ "sqrt"; ]
178+
[ "sqrt"; "caml_bswap16_direct"; "caml_int32_direct_bswap";
179+
"caml_int64_direct_bswap"; "caml_nativeint_direct_bswap" ]
184180

185181
let is_immediate n = n <= 0x7FFF_FFFF && n >= -0x8000_0000
186182

@@ -334,9 +330,13 @@ method! select_operation op args dbg =
334330
| _ ->
335331
super#select_operation op args dbg
336332
end
337-
| Cbswap { bitwidth } ->
338-
let bitwidth = select_bitwidth bitwidth in
339-
(Ispecific (Ibswap { bitwidth }), args)
333+
| Cextcall { func = "caml_bswap16_direct"; } ->
334+
(Ispecific (Ibswap 16), args)
335+
| Cextcall { func = "caml_int32_direct_bswap"; } ->
336+
(Ispecific (Ibswap 32), args)
337+
| Cextcall { func = "caml_int64_direct_bswap"; }
338+
| Cextcall { func = "caml_nativeint_direct_bswap"; } ->
339+
(Ispecific (Ibswap 64), args)
340340
(* Recognize sign extension *)
341341
| Casr ->
342342
begin match args with

‎backend/arm64/arch.ml‎

Lines changed: 3 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,6 @@ type addressing_mode =
4141
type cmm_label = int
4242
(* Do not introduce a dependency to Cmm *)
4343

44-
type bswap_bitwidth = Sixteen | Thirtytwo | Sixtyfour
45-
4644
type specific_operation =
4745
| Ifar_alloc of { bytes : int; dbginfo : Debuginfo.alloc_dbginfo }
4846
| Ifar_intop_checkbound
@@ -58,7 +56,7 @@ type specific_operation =
5856
| Imulsubf (* floating-point multiply and subtract *)
5957
| Inegmulsubf (* floating-point negate, multiply and subtract *)
6058
| Isqrtf (* floating-point square root *)
61-
| Ibswap of { bitwidth: bswap_bitwidth; } (* endianness conversion *)
59+
| Ibswap of int (* endianness conversion *)
6260
| Imove32 (* 32-bit integer move *)
6361

6462
and arith_operation =
@@ -104,11 +102,6 @@ let print_addressing printreg addr ppf arg =
104102
| Ibased(s, n) ->
105103
fprintf ppf "\"%s\" + %i" s n
106104

107-
let int_of_bswap_bitwidth = function
108-
| Sixteen -> 16
109-
| Thirtytwo -> 32
110-
| Sixtyfour -> 64
111-
112105
let print_specific_operation printreg op ppf arg =
113106
match op with
114107
| Ifar_alloc { bytes; } ->
@@ -170,8 +163,7 @@ let print_specific_operation printreg op ppf arg =
170163
| Isqrtf ->
171164
fprintf ppf "sqrtf %a"
172165
printreg arg.(0)
173-
| Ibswap { bitwidth } ->
174-
let n = int_of_bswap_bitwidth bitwidth in
166+
| Ibswap n ->
175167
fprintf ppf "bswap%i %a" n
176168
printreg arg.(0)
177169
| Imove32 ->
@@ -220,8 +212,7 @@ let equal_specific_operation left right =
220212
| Imulsubf, Imulsubf -> true
221213
| Inegmulsubf, Inegmulsubf -> true
222214
| Isqrtf, Isqrtf -> true
223-
| Ibswap { bitwidth = left }, Ibswap { bitwidth = right } ->
224-
Int.equal (int_of_bswap_bitwidth left) (int_of_bswap_bitwidth right)
215+
| Ibswap left_int, Ibswap right_int -> Int.equal left_int right_int
225216
| Imove32, Imove32 -> true
226217
| (Ifar_alloc _ | Ifar_intop_checkbound | Ifar_intop_imm_checkbound _
227218
| Ishiftarith _ | Ishiftcheckbound _ | Ifar_shiftcheckbound _

‎backend/arm64/emit.mlp‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -532,8 +532,8 @@ module BR = Branch_relaxation.Make (struct
532532
| Lop (Ispecific (Imuladdf | Inegmuladdf | Imulsubf | Inegmulsubf)) -> 1
533533
| Lop (Ispecific (Ishiftarith _)) -> 1
534534
| Lop (Ispecific (Imuladd | Imulsub)) -> 1
535-
| Lop (Ispecific (Ibswap { bitwidth = Sixteen } )) -> 2
536-
| Lop (Ispecific (Ibswap { bitwidth = (Thirtytwo | Sixtyfour) })) -> 1
535+
| Lop (Ispecific (Ibswap 16)) -> 2
536+
| Lop (Ispecific (Ibswap _)) -> 1
537537
| Lop (Ispecific Imove32) -> 1
538538
| Lop (Iname_for_debugger _) -> 0
539539
| Lop (Iprobe _ | Iprobe_is_enabled _) ->
@@ -898,15 +898,17 @@ let emit_instr i =
898898
| Imulsub -> "msub"
899899
| _ -> assert false) in
900900
` {emit_string instr} {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(2)}\n`
901-
| Lop(Ispecific(Ibswap { bitwidth })) ->
902-
begin match bitwidth with
903-
| Sixteen ->
901+
| Lop(Ispecific(Ibswap size)) ->
902+
begin match size with
903+
| 16 ->
904904
` rev16 {emit_wreg i.res.(0)}, {emit_wreg i.arg.(0)}\n`;
905905
` ubfm {emit_reg i.res.(0)}, {emit_reg i.res.(0)}, #0, #15\n`
906-
| Thirtytwo ->
906+
| 32 ->
907907
` rev {emit_wreg i.res.(0)}, {emit_wreg i.arg.(0)}\n`
908-
| Sixtyfour ->
908+
| 64 ->
909909
` rev {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}\n`
910+
| _ ->
911+
assert false
910912
end
911913
| Lop (Iname_for_debugger _) -> ()
912914
| Lop (Iprobe _ | Iprobe_is_enabled _) ->

‎backend/arm64/proc.ml‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -315,7 +315,6 @@ let operation_supported = function
315315
| Cclz _ | Cctz _ | Cpopcnt
316316
| Cprefetch _
317317
-> false (* Not implemented *)
318-
| Cbswap _
319318
| Capply _ | Cextcall _ | Cload _ | Calloc _ | Cstore _
320319
| Caddi | Csubi | Cmuli | Cmulhi _ | Cdivi | Cmodi
321320
| Cand | Cor | Cxor | Clsl | Clsr | Casr

‎backend/arm64/selection.ml‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,8 @@ let is_immediate n =
8787
(* If you update [inline_ops], you may need to update [is_simple_expr] and/or
8888
[effects_of], below. *)
8989
let inline_ops =
90-
[ "sqrt"; ]
90+
[ "sqrt"; "caml_bswap16_direct"; "caml_int32_direct_bswap";
91+
"caml_int64_direct_bswap"; "caml_nativeint_direct_bswap" ]
9192

9293
let use_direct_addressing _symb =
9394
(not !Clflags.dlcode) && (not Arch.macosx)
@@ -97,12 +98,6 @@ let is_stack_slot rv =
9798
| [| { loc = Stack _ } |] -> true
9899
| _ -> false)
99100

100-
let select_bitwidth : Cmm.bswap_bitwidth -> Arch.bswap_bitwidth =
101-
function
102-
| Sixteen -> Sixteen
103-
| Thirtytwo -> Thirtytwo
104-
| Sixtyfour -> Sixtyfour
105-
106101
(* Instruction selection *)
107102

108103
class selector = object(self)
@@ -232,9 +227,13 @@ method! select_operation op args dbg =
232227
| Cextcall { func = "sqrt" } ->
233228
(Ispecific Isqrtf, args)
234229
(* Recognize bswap instructions *)
235-
| Cbswap { bitwidth } ->
236-
let bitwidth = select_bitwidth bitwidth in
237-
(Ispecific(Ibswap { bitwidth }), args)
230+
| Cextcall { func = "caml_bswap16_direct" } ->
231+
(Ispecific(Ibswap 16), args)
232+
| Cextcall { func = "caml_int32_direct_bswap"; } ->
233+
(Ispecific(Ibswap 32), args)
234+
| Cextcall { func = "caml_int64_direct_bswap"; } |
235+
Cextcall { func = "caml_nativeint_direct_bswap" } ->
236+
(Ispecific (Ibswap 64), args)
238237
(* Other operations are regular *)
239238
| _ ->
240239
super#select_operation op args dbg

‎backend/cmm.ml‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -154,8 +154,6 @@ type trywith_kind =
154154
| Regular
155155
| Delayed of trywith_shared_label
156156

157-
type bswap_bitwidth = Sixteen | Thirtytwo | Sixtyfour
158-
159157
type memory_chunk =
160158
Byte_unsigned
161159
| Byte_signed
@@ -185,7 +183,6 @@ and operation =
185183
| Cstore of memory_chunk * Lambda.initialization_or_assignment
186184
| Caddi | Csubi | Cmuli | Cmulhi of { signed: bool } | Cdivi | Cmodi
187185
| Cand | Cor | Cxor | Clsl | Clsr | Casr
188-
| Cbswap of { bitwidth: bswap_bitwidth; }
189186
| Cclz of { arg_is_non_zero: bool; }
190187
| Cctz of { arg_is_non_zero: bool; }
191188
| Cpopcnt

‎backend/cmm.mli‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -152,8 +152,6 @@ type trywith_kind =
152152
This allows for sharing a single handler in several places, or having
153153
multiple entry and exit points to a single trywith block. *)
154154

155-
type bswap_bitwidth = Sixteen | Thirtytwo | Sixtyfour
156-
157155
type memory_chunk =
158156
Byte_unsigned
159157
| Byte_signed
@@ -166,6 +164,7 @@ type memory_chunk =
166164
| Single
167165
| Double (* word-aligned 64-bit float
168166
see PR#10433 *)
167+
169168
and operation =
170169
Capply of machtype * Lambda.region_close
171170
| Cextcall of
@@ -186,7 +185,6 @@ and operation =
186185
| Cstore of memory_chunk * Lambda.initialization_or_assignment
187186
| Caddi | Csubi | Cmuli | Cmulhi of { signed: bool } | Cdivi | Cmodi
188187
| Cand | Cor | Cxor | Clsl | Clsr | Casr
189-
| Cbswap of { bitwidth: bswap_bitwidth; }
190188
| Cclz of { arg_is_non_zero: bool; }
191189
| Cctz of { arg_is_non_zero: bool; }
192190
| Cpopcnt

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