A change by DavidSpickett · Pull Request #58 · DavidSpickett/llvm-project

DavidSpickett · 2023-11-15T13:00:33Z

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github-actions · 2023-11-15T13:00:47Z

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github-actions · 2023-11-15T13:05:39Z

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github-actions · 2023-11-15T13:05:45Z

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) Currently, process of replacing bitwise operations consisting of `LSR`/`LSL` with `And` is performed by `DAGCombiner`. However, in certain cases, the `AND` generated by this process can be removed. Consider following case: ``` lsr x8, x8, #56 and x8, x8, #0xfc ldr w0, [x2, x8] ret ``` In this case, we can remove the `AND` by changing the target of `LDR` to `[X2, X8, LSL #2]` and right-shifting amount change to 56 to 58. after changed: ``` lsr x8, x8, #58 ldr w0, [x2, x8, lsl #2] ret ``` This patch checks to see if the `SHIFTING` + `AND` operation on load target can be optimized and optimizes it if it can.