Mutually exclusive enable for TMUX1108 (8:1) and TMUX1104 (4:1) using SN74LVC1G240 — safe POR and logic review

You are trying to have a single digital line that can only be either high or low express three states. That's not going to work.

You have a total of 13 output states you want to select between (one of 12 analog signals, and high impedance). That requires a minimum of 4 digital signals one way or another, since 3 signals can only express 8 different states.

One way to use the four digital control signals is as four address lines. Since the firmware is driving the address lines, the mapping of the 0-15 address to the output state can be arbitrary.

If you connect the low three address lines ADR2-ADR0 to the address inputs of the 8:1 mux, and ADR3 to its enable, then that mux will only respond to addresses 8-15. Its output will be high impedance for addresses 0-7.

For the 4:1 mux connect ADR1-ADR0 to its address inputs, and the NOR of ADR3 ad ADR2 to its enable. That means it will only respond to addresses 0-3.

With the above scheme, addresses 4-7 will cause the overall output to be high impedance. Pull ups and downs on the two high address lines will guarantee high impedance unless the address lines are explicitly driven.

As stated earlier, you'll need a minimum of 4 digital outputs from your processor. If you can afford one more digital output, then you can get rid of the logic gate to make the 4:1 mux enable signal and drive both enables directly from the micro instead. That simplifies things, and leaves the control completely to the firmware. This is what I would do unless there really are only 4 digital outputs available for this task.

I am not trying to encode 13 output states using a single digital line.

Right. Like I said, you are trying to encode 3 states with your single digital line WE_MUX_EN. Those states are mux 1 enabled, mux 2 enabled, and neither mux enabled.

My requirement is simply mutual exclusion between two multiplexers

If you read my answer more carefully, you will see that's exactly what it gets you. With the 4-wire solution, addresses 8-15 select mux 1, 0-3 select mux 2, and the remaining addresses 4-7 select neither. With the 5-wire solution, you have explicit control over enabling each mux independently.

That is why I am using the same address lines and a single control signal (with inversion) for the enable pins—not to increase the number of selectable states, but only to choose which MUX is active.

By thinking of the problem that way, you get into the confusion that caused you to ask the question. I show a different way of thinking of the overall problem such that simpler solutions are more apparent. In the 4-wire option (same number of control lines as yours), only a single NOR gate is needed. The 5-wire option uses one more control line, but requires no additional logic.

posted 11 days ago

CC BY-SA 4.0

9d ago

Olin Lathrop‭

9092 reputation 18 400 1080 505

Hello, happy new year.

Nice Shematic. To be honest, it should not work as posted. The reason being, according to the SN74LVC1G240 datasheet, when both pins 1 (NOT_OE), and 2 (A) are low, the output (Y) is High. This would enable the 4:1 MUX at every Power-On.

Instead, you could use two D-Type FlipFlops as a binary counter; Connect the FlipFlops as a binary counter (picture bellow); Connect both FlipFlop's CLK inputs to WE_MUX_EN from the AD5941; Connect each MUX_EN to a different FlipFlop Q output.

At power on, if WE_MUX_EN is low, both FlipFlop's outputs are off. When the firmware pulls WE_MUX_EN High, the first MUX turns ON; On the next WE_MUX_EN High, the first MUX turns OFF, and the second turns ON; To alternate MUXes, simply pulse WE_MUX_EN High.

Dual D-Type FlipFlop as binary counter

posted 12 days ago

CC BY-SA 4.0

eric.uribatake‭

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