RTC battery and VCC switching circuit
The circuit shown below is used on one of my PCBs to switch the VBAT supply for the RTC, ensuring timekeeping continues whenever the main supply (VCC) is unavailable.
Circuit Operation
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Under normal conditions, when VCC is available, VBAT is powered through D1.
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When VCC is removed, VBAT is instead supplied by the coin cell through P1 and Q1. This behavior matches the intended design.
Issue Observed
- After about a month in use, the RTC coin cell (nominally 3 V) was found discharged to 1.6 V. This is unexpected, since such batteries are typically expected to last several years in standby applications.
Measurements
With VCC present:
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VBAT = 3.117 V
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Current = –2.25 mA (appears to flow into the coin cell).
With VCC absent:
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VBAT = 2.893 V
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Current = ~16 µA
I’m not fully certain if Q1’s biasing is the root cause, but it seems probable given the reverse current flow when VCC is present.
Edit: I checked the STM32 datasheet and the MCU has inbuilt switching mechanism. I don't think the external switching will be required.
I came across another point in the application note which says -
Can I use BAS716 diode? It’s a low-leakage small-signal silicon diode in SOD-523. Nexperia specifies very low reverse current (typ ~0.2 nA) and 75–85 V reverse rating; it’s designed for low-leak applications.
At the tiny RTC currents (µA range), the forward drop of a silicon switching diode is modest (well below the 1.25 V quoted at high test currents).
link - https://www.digikey.com/en/products/detail/nexperia-usa-inc/BAS716-115/1232107
There is another option of using P-MOSFET with drain connected to BATTERY+ and Source connected to VBAT pin and Gate is shorted to Source. The body diode (D→S) blocks reverse current from VBAT back into the cell, but allows forward current from the cell into VBAT with only milliohms of drop once the FET turns on.
Which is better suited for long coin-cell life ?
1 answer
You are using a P-channel MOSFET. Pin 2 is the source, pin 3 the drain, and pin 1 the gate.
Note that the gate is only raised to ¾ of the input voltage when the 3.3V input is active. You didn't supply a link to the FET datasheet, so you need to check what kind of leakage is expected in that case.
If that doesn't explain what you see, then you probably have the drain and source of Q1 flipped.
Another problem is the way you draw schematics. Obfuscating the circuit not only makes it more difficult for others to follow, but more likely you will make a mistake. If you had drawn it more reasonably, you might have caught the mistake where the left end of R2 was connected in your previous question. R1 and R2 are still a mess. If you drew the schematic cleanly you might notice there is a better topology.
Asking others to look at a messy schematic is not respecting their time and effort. If you don't care, why should I?
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