Securing today’s systems from tomorrow’s threats.
About Us
RAE, LLC is a non-traditional defense contractor committed to offering innovative and flexible solutions to sectors that demand the highest standards of security and functionality. Our team’s expertise spans Systems Architecture Design and Systems Architecture Security Assessment, ensuring that every solution we create is both efficient and resilient to modern cybersecurity threats.
What sets us apart is our unique focus on security-first system design, which is essential for organizations dealing with sensitive data and complex environments. We understand the critical nature of compliance and reliability in government and defense projects, as well as the evolving security needs of commercial enterprises. Our services are designed to ensure long-term operational success, with integrated security solutions built from the ground up.
Our Security IP
PROTECT
PROTECT IP is a patent-pending solution to enable the post-quatum resistant secure boot of commodity FPGA-based products.
Deployable in both existing and future FPGA-based products.
Removes need for “burned-in” keys.
Enables in-field reconfiguration of associated FPGA bitstream.
Enforces integrity protections without relying upon asymmetric cryptography.
Novel PUF usage to “recreate” rather than derive key material.
Configuration lock ensure unauthorized entities cannot dis-enroll or re-enroll products.
Foundation for a “blank-slate” security solution enabling ITAR restricted design in commercial systems.
AES Crypto
Patent-pending AES core with integrated PUF solution for masking and obfuscating power signatures used in SPA/DPA attacks.
Injects random data generated by PUF into every operations.
Randomly exchanges valid and bogus data between dual instances running in lock-step.
Encryption/decryption of the exact same block will always have a different power signature, both across reboots and throughout run-time.
Deployable as VHDL block on most FPGA products.
Integrates with any PUF or PUF-based TRNG.
Our Services
Altera FPGA Security Consulting
Anti-tamper Solution Architecture
Anti-tamper Solution Evaluation
Attack-Countermeasure Tree Development
Attack-Countermeasure Tree Documentation
Chiplet Security Design Consulting and Engineering
Cryptographic Agility Design and Consulting
Cryptographic IP Development and Licensing
Cryptographic System Assessment
Cryptographic System Design
General Computing Systems Design and Consulting
Intel Processor-based System Design Consulting
Intel Processor Security Consulting
Key Management Plan Development
Key Management Plan Documentation
Microchip FPGA Security Consulting
PUF Design Consulting and Engineering
PUF IP Development and Licensing
Secure Boot Design and Consulting
Systems Architecture Design
Systems Architecture Security Assessment
System Security Design
Our Customers
Our People
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CTO
Dr. Areno completed his Bachelor’s and Master’s degrees at Utah State University in 2007 and took a position with Sandia National Laboratories. At Sandia, he focused on vulnerability assessment and reverse engineering of embedded systems primarily utilizing ARM-core processors. During this time, he also completed his PhD at the University of New Mexico with dissertation work on strengthening embedded system security through the use of PUF-enhanced cryptographic units. In 2013, Dr. Areno took a position with Raytheon Cyber Security Innovations in Austin, TX; he served as a Chief Architect for a number of anti-tamper solutions, with specific expertise in establishing trust in COTS equipment. In 2019, he joined Intel where he served as a Senior Principal Engineer and had roles including the Senior Director of Security Assurance and Cryptography, Chief Security Architect, and Anti-Tamper Lead. Dr. Areno serves on the Board of Advisors for Augusta University School of Computer and Cyber Sciences, as the co-chair of the Secure Edge Working Group under the Midwest ME-Commons Consortium, and on the Editorial Board for the Journal of Hardware and Systems Security.
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Principal Design Engineer
Trevor Hird joined Rickert-Areno Engineering in early 2026 as a Principal Design Engineer with 18 years of engineering experience across FPGA design, security architecture, and vulnerability research in the US Defense electronics and cybersecurity space. Prior to joining RAE, Trevor was a Technical Fellow at Nightwing CODEX, managing the Texas engineers and leading vulnerability research and root-of-trust development efforts.
Trevor received his B.S. in Electrical and Computer Engineering from The University of Texas at Austin, where he was a Cockrell Scholar, and his M.S. in Electrical Engineering (Computer Architecture focus) from the University of Southern California. Mr. Hird worked at Raytheon Company (and its resulting merged company RTX) for over 15 years, followed by Nightwing, which is the product of a divestment of RTX’s Cybersecurity and Intelligence Solutions business sold to Blackstone.
Trevor holds two US Patents in the hardware security domain.
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Owner & CEO
Cylinda is the CEO responsible for business operations including personnel, finances, contracts, compliance, project management, communications, and culture. Cylinda received her BA in Communications with a concentration in Journalism from Marist University in Poughkeepsie, NY.
With years of service on volunteer boards for non-profits and her ties to the community through music performance, Cylinda has a deep sense of civic responsibility and a strong passion for the arts. Board work has made her a great listener, a natural collaborator, and someone who seeks to understand and uplift others.