OpenROAD is the leading open-source, foundational application for semiconductor digital design. It eliminates the barriers of cost, risk and uncertainty in hardware design to foster open access, expertise, rapid innovation, and faster design turnaround. The OpenROAD flow delivers an autonomous, no-human-in-the-loop, 24 hour turnaround from RTL to GDSII for design exploration and physical design implementation.
External link for The OpenROAD Project
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The OpenROAD Project reposted this
Here are the slides of my keynote at Design, Automation and Test in Europe Conference (DATE) 2026. Great event! Thanks to the organizers and a special thanks to Valeria Bertacco as General Chair. Also for the content of my presentation I owe a lot to Frank Kagan Gurkaynak Stefan Wallentowitz and PULP Platform https://lnkd.in/e7JTPM9U
The OpenROAD Project reposted this
ElemRV-N 0.3 - next generation of the open-source RISC-V chip taped out! The third revision of ElemRV has been taped out, bringing significant performance and architecture improvements to this end-to-end open-source RISC-V microcontroller. ⚡ ElemRV-N 0.3 introduces dedicated L1 data and instruction caches, and the chip clock now runs at 60 MHz - 3x the previous revision - with the CPU and peripherals operating at 30 MHz. The SPI controller now supports Quad I/O, and both the SPI flash and HyperBus controllers feature burst transfer capabilities. The HyperBus controller now achieves 60 MB/s throughput. The bus architecture has been migrated from AMBA to BMB and Wishbone - removing the dependency on ARM IP and keeping the entire design fully open-source. 🔓 This revision also adopts a hierarchical design, with the CPU, HyperBus, and SPI flash controller placed in dedicated macros. This was a necessary step toward making ElemRV an asynchronous design - once an open-source PLL becomes available, the pieces will be in place. The full project is open-source and built entirely with SpinalHDL and the The OpenROAD Project toolchain, targeting the IHP – Leibniz Institute for High Performance Microelectronics SG13G2 PDK. A big thank you to Krzysztof Herman and Norbert Herfurth at IHP for their support in making this tape-out possible! 🙏 If you're interested in following the journey toward making ElemRV production-ready, check out the project here: 🔗 https://lnkd.in/gtDMrqqb #RISCV #OpenSource #ChipDesign #ASIC #TapeOut #VLSI #OpenHardware #SpinalHDL #OpenROAD #SemiconductorDesign #EmbeddedSystems #HardwareEngineering
The OpenROAD Project reposted this
[ENG] Polish processors are here and they’re fast! ChipCraft built a polish processor #RISCV (#polishProcessor, #polskiProcesor) from scratch. Synthesized in 7nm finFET ASAP7 technology it reaches 1.5 GHz! Full control over the source code means zero backdoors what is perfect for defense and high-security applications. #OpenSource is a game-changer. A few years ago, who imagined #Verilator supporting #UVM, or #OpenROAD delivering full RTL-to-GDS flow? Our processors CC-RV32ST-C and CC-RV32HR-C are fully Verilator-ready. Start testing our processors today with our free SDK/IDE and cycle-accurate simulation, without needing any hardware. OpenROAD PDK opens the door to many new opportunities. CEZAMAT WUT, let’s make it together! Explore more/Dowiedź się więcej: • CC-RV32ST-C (https://bit.ly/4tJGbOU) • CC-RV32HR-C (https://bit.ly/4cldyAq) • SDK/IDE (Windows: https://bit.ly/3ObQlZu, Linux: https://bit.ly/4dCdrTn) [PL] Polskie procesory są gotowe i szybkie jak nigdy! #ChipCraft zbudował polski procesor #RISCV (#PolskiProcesor, #PolishProcessor) całkowicie od podstaw. Synteza w technologii 7nm finFET ASAP7 pozwala osiągnąć częstotliwość pracy 1,5 GHz! Pełna kontrola nad kodem źródłowym oznacza zero backdoorów, co czyni je idealnymi dla przemysłu obronnego i zastosowań wymagających najwyższego poziomu bezpieczeństwa. #OpenSource zmienia zasady gry. Jeszcze kilka lat temu nikt nie wyobrażał sobie, że #Verilator będzie wspierał #UVM, a #OpenROAD zapewni pełny proces projektowy RTL do GDS. Nasze procesory CC-RV32ST-C i CC-RV32HR-C w pełni obsługują symulacje w Verilator. Rozpocznij testy już dziś dzięki naszemu darmowemu SDK/IDE z wbudowanym symulatorem typu „cycle-accurate” bez konieczność posiadania fizycznego procesora. OpenROAD PDK otwiera drzwi do wielu nowych możliwości. #CEZAMAT, zróbmy to razem! #semiconductor #ICdesignServices #ICdesign #ASICdesign #FPGAdesign #ASIC #IC #FPGA #IP #IPcore #IPblock #RISCV #embedded #processor #SoC #MCU #IDE
The OpenROAD Project reposted this
Great platform for students and enthusiasts to get their hands on the whole IC design flow for free!! Mentored by a world class team from across the globe. Last year we had a team of undergraduates from Silicon University (Silicon Institute of Technology (SIT), Bhubaneswar) design standard cells for a open source library, tapeoout and now in the process of packaging and testing. This is the kind of experience needed to convert them from students to engineers!
Build It. Test It. Publish It. The 2026 SSCS PICO Chipathon is LIVE! Are you ready to take your IC design from a repository to real-world silicon? The IEEE Solid-State Circuits Society is thrilled to announce the next edition of the SSCS PICO Open-Source Chipathon! 🏔️⚡ This isn't just a design contest; it’s a full-flow journey from specification to silicon measurements. Sponsored by the OpenROAD Initiative, we are fostering the #OpenEDA ecosystem by inviting you to contribute to a global library of reusable building blocks. Why Join? ✅ Mentorship: Work with experienced industry and academic experts. ✅ Full Lifecycle: Experience onboarding, design reviews, tapeout, and post-silicon measurement. ✅ Open Tools: Utilize the GF180MCU open PDK and the OpenROAD toolchain. ✅ Publication: Opportunities to present your work at a dedicated workshop and via peer-reviewed papers. Choose Your Track: 🔹 Track A: Foundational Blocks (Analog/Digital IP) 🔹 Track B: Circuits for Sensors (Edge-native systems & MEMS) 🔹 Track C: MOSbius (Hands-on "Learn-by-measurement" playground) 🔹 Track D: AI/LLM-Assisted Circuits (Agentic flows & automated generation) Who can participate? Anyone! We especially encourage pre-college students, undergraduates, and designers from underrepresented regions. No prior tapeout experience is required. 📅 Sign-up Deadline: May 1, 2026 🔗 Register & Learn More: https://bit.ly/4bT2SKm Let's build the future of open-source silicon together! 🛰️💻 #IEEESSCS #OpenSource #Chipathon #ICDesign #PICO #OpenROAD #Semiconductors #AIHardware #AnalogDesign #CircuitDesign #IEEE
The OpenROAD Project reposted this
This is a great and a popular platform for practical chip design--digital, analog, mixed signal using open-source EDA tools leveraging innovation in EDA, AI-augmented EDA and new tools. This program is well supported by experienced mentors across academia and industry, who are committed to sharing their expertise and resources towards delivering program objectives and success. This year, the OpenROAD Initiative The OpenROAD Project is a proud sponsor! Stay tuned! Tom Spyrou Mehdi Saligane IEEE Solid-State Circuits Society (SSCS). Join us on Discord : https://lnkd.in/gZjWUu-v.
Build It. Test It. Publish It. The 2026 SSCS PICO Chipathon is LIVE! Are you ready to take your IC design from a repository to real-world silicon? The IEEE Solid-State Circuits Society is thrilled to announce the next edition of the SSCS PICO Open-Source Chipathon! 🏔️⚡ This isn't just a design contest; it’s a full-flow journey from specification to silicon measurements. Sponsored by the OpenROAD Initiative, we are fostering the #OpenEDA ecosystem by inviting you to contribute to a global library of reusable building blocks. Why Join? ✅ Mentorship: Work with experienced industry and academic experts. ✅ Full Lifecycle: Experience onboarding, design reviews, tapeout, and post-silicon measurement. ✅ Open Tools: Utilize the GF180MCU open PDK and the OpenROAD toolchain. ✅ Publication: Opportunities to present your work at a dedicated workshop and via peer-reviewed papers. Choose Your Track: 🔹 Track A: Foundational Blocks (Analog/Digital IP) 🔹 Track B: Circuits for Sensors (Edge-native systems & MEMS) 🔹 Track C: MOSbius (Hands-on "Learn-by-measurement" playground) 🔹 Track D: AI/LLM-Assisted Circuits (Agentic flows & automated generation) Who can participate? Anyone! We especially encourage pre-college students, undergraduates, and designers from underrepresented regions. No prior tapeout experience is required. 📅 Sign-up Deadline: May 1, 2026 🔗 Register & Learn More: https://bit.ly/4bT2SKm Let's build the future of open-source silicon together! 🛰️💻 #IEEESSCS #OpenSource #Chipathon #ICDesign #PICO #OpenROAD #Semiconductors #AIHardware #AnalogDesign #CircuitDesign #IEEE
The OpenROAD Project reposted this
Silicon democratization cannot be stopped! 👍
What if one person could build an entire chip from scratch — without Synopsys, Cadence, or Siemens? I did it. A complete RISC-V RV32IM CPU — from behavioral Verilog to tape-out ready GDSII — using a synthesis engine I built myself from scratch in C++. No commercial EDA licenses. No team. No funding. Just engineering. What's inside: → 5-stage pipelined RV32IM with full forwarding, branch prediction (BHT+BTB), and machine-mode CSR → Self-made synthesis tool: AIG optimization, NPN Boolean matching, SAT-based formal verification, retiming, multi-corner STA → 33,053 cells mapped to 37 SKY130 cell types → 92/92 ISA compliance tests passing before synthesis → Every signoff clean: DRC 0, LVS 0, Antenna 0, IR Drop 0.01% → Two designs proven through the same flow — RISC-V (33K cells, 40 MHz) + FIR filter (47K cells, 100 MHz) This isn't a simulation. This isn't an FPGA bitstream. This is real silicon-ready GDSII on SkyWater 130nm. The EDA industry tells you chip design requires million-dollar tools and hundred-person teams. I built a dependency-free C++ synthesis engine that takes behavioral Verilog and produces production-quality netlists — then pushed it through open-source PnR to clean GDSII. Twice. The attached PDF has the full breakdown — architecture, tool flow, PPA metrics, layout images, signoff results, and competitive analysis against 35+ open-source RISC-V implementations. What's next: → 8x8 INT8 Systolic Array (AI accelerator through the same flow) → RISC-V + Neural Network accelerator on one chip → Efabless chipIgnite tapeout for real silicon Semiconductor design should belong to everyone — not just those who can afford the tools. If you're working on open-source EDA, RISC-V, or silicon engineering — let's connect. If you're building something and need someone who can go from RTL to GDSII solo — let's talk. Open to research collaborations. RISC-V International Matt Venn Tiny Tapeout IHP – Leibniz Institute for High Performance Microelectronics University of California, Berkeley SiFive Luca Benini David Wentzlaff Subhasish Mitra Christopher Batten Ali M. Niknejad Andreas Olofsson ETH Zurich, Department of Information Technology and Electrical Engineering Technical University of Delft Bluespec, Inc Codasip ChipFlow Agile Analog Akeana Axelera AI Analog Devices The OpenROAD Project FOSSi Foundation OpenFive Open-Silicon, Inc. @ #RISCV #ChipDesign #OpenSource #EDA #VLSI #ASIC #Semiconductor #SKY130 #RTLtoGDSII #SiliconEngineering #OpenSourceHardware #CustomSynthesis #GDSII #TapeOut
The OpenROAD Project reposted this
India’s #First #OpenSource #RISC-V #SoC on #Indigenous #SCL180 PDK Has #Taken Shape A major milestone for India Semiconductor Mission ecosystem. We have now built a #Caravel-style RISC-V SoC shell and core using entirely open-source EDA tools with indigenous SCL180 PDK collateral. This is a strong step toward reducing one of the biggest barriers in Indian chip design: the cost and inaccessibility of proprietary design infrastructure. #Why this #matters? India’s semiconductor mission cannot rely only on manufacturing ambition. It also needs accessible design infrastructure, reusable SoC templates, practical silicon workflows, and a generation of engineers who can build chips with confidence. When chip design depends heavily on expensive proprietary tools, the entry barrier for startups, research labs, and academic institutes remains very high. This work shows a different path. With open-source tools and indigenous PDK support, Indian startups can begin experimenting with SoC architecture, floorplanning, integration, harness design, and full-chip assembly without waiting for large budgets. Indian institutes can start building RISC-V based SoCs, train students on realistic design flows, and create real project ecosystems around chip design rather than limiting learning to theory. What has been achieved so far: - A serious Caravel-style shell and core hierarchy on SCL180 - A legal padframe-based top-level floorplan with chip_io - A frozen core-and-shell floorplan with management, user, housekeeping, clocking, PLL, and IO support macros integrated - A complete flow built using open-source tools and indigenous process collateral Tools used in this exercise include: - OpenLane - OpenROAD - KLayout - Python/Tcl-based open flow scripting Why this is important for India: - Lower entry barrier for Indian chip design startups - Stronger RISC-V based SoC development ecosystem - A practical path for institutes to start full-chip SoC education and research - Greater self-reliance in design enablement using indigenous PDK infrastructure - A foundation for reusable open silicon platforms built in India This is not the end. Tapeout and testing are yet to be done. Stay tuned. Also, #opening the #user_project_area for more user projects is coming soon. This is the kind of infrastructure work that can quietly change who gets to #build #chips in #India. Thanks each and everyone of you in below list who were directly or indirectly involved and inspired/motivated VLSI System Design (VSD) to make this happen Nishit Gupta Uday Khambete Deb Malik Sharat Kaul Amitesh Kumar Sinha Indira Iyer Almeida Mohamed Kassem Samir Patel Indian Institute of Technology Gandhinagar Ministry of Electronics and Information Technology India Electronics and Semiconductor Association Digital India RISC-V (DIR-V) Program The OpenROAD Project RISC-V International
The OpenROAD Project reposted this
Heads up! I'm moving openroad-demo into bazel-orfs/gallery. The gallery is used as data for a Flow Rules Checker I'm working on. If you ask for a 8000x8000um floorplan because you set CORE_UTILIZATION work, OpenROAD will give it to you. You asked for it, you deserve the result. It is not the job of OpenROAD to tell you that your intent is wrong. The Flow Rules Checker will check intent and run through the entire flow in seconds and produce a report that will avoid having to wait for hours and hours to figure out that you missed a spot in your parameters of the flow. https://lnkd.in/ducD-35Q https://lnkd.in/e26HJMXE
Most open source projects fail not because the code was bad, but because they stopped doing what was needed. Here's a git workflow that fixes that - using Claude. The problem with PRs: - Reviewing code is hard - Merge conflicts are stressful - A contributor with a good idea and a bad PR gets rejected - The idea is lost The insight: - Reviewing a feature request is easy - Discussing intent is calm - Execution is now free The flow: 1. Contributor opens a PR - rough code, good idea 2. Maintainer extracts the intent → Feature Request, stored in git with authorship 3. FR is discussed, scoped, refined - no stress, no merge conflicts 4. Claude implements the FR → clean PR5. Merge The contributor who had the idea is the author. Claude is labor The rules are simple: PR → FR → PR: always safe FR → PR: always safe Merging a foreign PR directly: risky Foreign PR → FR → PR: safe again Why it works: Code has no intrinsic value when Claude can generate it freely. Ideas do. A protected, well-scoped FR that solves a real problem is where value lives. Shift your quality gate from code to intent. Let Claude handle the execution gap. Keep the idea author's name on the work. Stress is now optional.
The OpenROAD Project reposted this
Daniel Schultz, founder of aesc silicon, talked about his fully open source chip development, at World RISC‑V Days Turin event organized by us on 26 February 2026. Schultz demonstrates that it is now possible to create fully open source chips, from core design to silicon fabrication! By leveraging open source RTL and EDA tools, Schultz's work culminates in projects like ElemRV, an end-to-end open-source microcontroller built around a RISC-V core. His talk showcased how the openness of the RISC-V ISA enables a new paradigm of hardware development, which he describes as "bringing the proven success of Linux to the semiconductor industry," empowering individuals and organizations to simulate, implement on FPGA, and manufacture their very own ASICs. Did you miss it? Worry not! We recorded all the talks! Watch it here: https://lnkd.in/dVPv6WkW #RISCVEverywhere
The OpenROAD Project reposted this
I built an OpenROAD Demo Gallery with Claude skills https://lnkd.in/eksRpMsR Install Bazelisk, ask Claude to "/demo-add <url>" and the project is added to the gallery. The repo is tiny — just config, constraints, and patches. Bazel fetches everything else: RTL source, OpenROAD, PDKs. No Docker, no system compilers. Each project doubles as a regression test for the OpenROAD flow. PRs adding new designs are welcome. #OpenSource #ChipDesign #ASIC #OpenROAD #RISCV #EDA
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