Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

Since the 1990s reusable functional blocks, well known as IP-Cores, were integrated on one silicon die. These Systems-on-Chip (SoC) used a bus-based system for intermodule communication. Technology and flexibility issues forced to introduce a novel communication system called Network-on-Chip (NoC). Around 1999 this method was introduced and until then it is investigated by several research groups with the aim to connect different IP-Blocks through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for a multi-layer Network-on-Chip and the related techniques for adapting the network while run-time to the requirements of an application.