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Martin Zabel's user avatar
Martin Zabel's user avatar
Martin Zabel's user avatar
Martin Zabel
  • Member for 10 years, 3 months
  • Last seen more than 2 years ago
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About

I'm a software engineer at MaibornWolff. Formerly, I was a teacher and research scientist at the Technische Universität Dresden, Germany. I'm also one of the authors of the PoC-Library on GitHub.

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Top posts

View all questions, answers, and articles
answer
13
copy data from kernel space to user space
Dec 8, 2015
answer
13
wait statement must contain condition clause with UNTIL keyword
Nov 18, 2015
answer
12
Unable to write on /dev/* files
Dec 30, 2015
answer
8
Calculating the Overflow Flag in an ALU
Dec 30, 2015
answer
6
x86 Intel Assembly and C++ - Stack around array corrupted
Nov 18, 2015
answer
5
vsim does not accept -modelsimini parameter on Windows
May 4, 2016
answer
4
Does the CONSTANT declaration stores the values in Block-RAM or in flipflops of an FPGA?
Feb 29, 2016
answer
4
VHDL behavioural D Flip-Flop with R & S
Jan 5, 2016
answer
4
MPI_Gather 2D array
Dec 31, 2015
answer
4
_mm_sad_epu8 faster than _mm_sad_pu8
Dec 28, 2015

Top Meta posts

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19
Accidentally edited a low-quality answer, what should I do?
9
Should "quartus" and "quartus-ii" be synonyms?

Top network posts

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9
Do I need to reset my FPGA design after startup?
7
VHDL simulation shows 'X' for input
7
Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code
5
Do I need to reset my FPGA design after startup?
5
Why is D flip-flop positive edge triggered instead of level triggered?