I need 2 clocks running at different frequencies. I tried:

forever
begin
 #5ns clk1=~clk1;
 #4ns clk2=~clk2;
end

clk2 will generate after clk1 is done, but they wont generate at the same time. Is there anyway to make it work?

I need 2 clocks running at different frequencies. I tried:

forever
begin
 #5ns clk1=~clk1;
 #4ns clk2=~clk2;
end

With this code, clk2 will generate after clk1 is done, but they won't generate at the same time.

How can I write the Verilog code to ensure that the two clocks (clk1 and clk2) will generate at the same time?

I need 2 clock working with different frequency.

but if I wrote like

forever
begin
 #5ns clk1=~clk1;
 #4ns clk2=~clk2;
end

clk2 will generate after clk1 is done, they wont generate at the same time. is there anyway to make it work?

I need 2 clocks running at different frequencies. I tried:

forever
begin
 #5ns clk1=~clk1;
 #4ns clk2=~clk2;
end

clk2 will generate after clk1 is done, but they wont generate at the same time. Is there anyway to make it work?